Abstract: A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.

Abstract: A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.

Abstract: A method of adhering copper thin film to a substrate in an integrated circuit structure includes preparing a substrate, including forming active regions and trenches for interconnect structures; depositing a metal barrier layer on the substrate; depositing an ultra thin film layer of tungsten over the barrier metal layer; depositing a copper thin film on the tungsten ultra thin film layer; removing excess copper and tungsten to the level of the metal barrier layer; and completing the integrated circuit structure.

Abstract: A method is provided for maintaining profiles in a device store. The method comprises: setting a profile type; selecting profile parameters such as destinations and processes; adding the profile to a device store; and, in response to creating the profile, limiting the lifetime of the profile in the device store. Time aging profiles, single-use profiles, renewable profiles, and permanent profiles can be selected. When a time aging profile is chosen, a time-to-live (TTL) variable, referenced to the creation of the profile, is also selected. Then, the profile is purged from the store when the TTL variable expires. When a single-use profile is chosen, the profile is purged from the store after the profile is used a first time. When a renewable profile is chosen, a TTL variable is selected that is reset in response to using the profile. The profile is purged from the store if the TTL variable expires.

Abstract: A thin film transistor includes an active silicon layer deposited by physical vapor deposition (PVD), wherein a silicon precursor is doped with impurities prior to use as a target in the PVD chamber, wherein the precursor has a resistivity in the range of about 0.5 &OHgr;-cm<&rgr;s<60 &OHgr;-cm; and wherein the target includes plural, rectangular tiles wherein all individual tiles are larger than 8.5 inches square.

Abstract: A color field sequential projector includes an electronically controllable quarter waveplate positioned between a reflection device and a polarized light beam splitter, wherein the controllable quarter waveplate is switched to be optimum for particular wavebands as the illumination distribution changes during a color field sequence. The electronically controllable quarter waveplate provides for improved contrast performance and color purity in the projected image.

Abstract: A system and method are provided for reducing film surface protrusions in the fabrication of LILAC films. The method comprises: forming an amorphous film with a first thickness; annealing the film using a LILAC process, with beamlets having a width in the range of 3 to 10 microns; in response to annealing, forming protrusions on the film surface; optionally oxidizing the film surface; thinning the film; and, in response to thinning the film, smoothing the film surface. Typically, the film surface is smoothed to a surface flatness of 300 Å, or less. In some aspects of the method, oxidizing the film surface includes oxidizing the film surface to a depth. Then, thinning the film includes thinning the film to a third thickness equal to the first thickness minus the depth.

Abstract: A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sources of all transistors in a column of the array; and a set of second bit lines connecting the drains of all transistors in a column of the array; wherein the ferroelectric stack has opposed edges, which, when projected to a level of the source, drain and channel, are coincident with an abutted edge of the source and the channel and the drain and the channel, respectively.

Abstract: An MRAM device includes a substrate; plural conductive lines, including a bit line and a word line; and a MTJ stack including a pair of magnetic yoke structures, wherein each of said yoke structures surrounds a conductive line. A method of fabricating a magnetic yoke in an MRAM structure includes preparing a substrate; forming a first conductive line on the substrate; fabricating a MTJ stack, including fabricating a first magnetic yoke structure about the first conductive line; forming a second conductive line on the MTJ stack; fabricating a second magnetic yoke about the second conductive line; depositing a layer of oxide on the structure; and metallizing the structure.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; amorphizing the Si1−XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator; a passivation oxide layer located over the substrate and gate stack; and metalizations to form contacts to the active regions and the gate stack.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: A method of coordinating the delivery of two independent messages, of different mediums, for simultaneous presentation is provided. The messages are communicated in a system capable of including coordination plans with the messages. The coordination plans include the identity of the independent messages, points in the messages where the coordination begins, and the duration of the presentation. Once linkage points in the first and second messages are defined, the relationship between messages is defined, so that independent messages 10 are displayed with predefined, meaningful timing. In communication system flexible enough to support real-time, two-way communications, such as wireless telephones, at least one of the messages to be coordinated can be received and presented in real-time. A system of coordinating two independent messages with a coordination plan message is also provided.

Abstract: A Home Network telephone system and method are provided for backing up user data. The system comprises at least one endpoint to transceive telephone communications. The endpoints can be devices such as telephones or fax machines, for example. The system also comprises a gateway to service and transceive telephone communication with the endpoints. The gateway has a memory to store a copy of user data associated with each endpoint. The gateway stores user data such as telephone directories, calling line ID (CLID) lists, call-logs, and user preferences for organizing the stored data. The gateway can supply the endpoints with an initial start-up configuration of user data, or resupply an endpoint in response to the endpoint losing the copy of the user data stored in its local memory. Each endpoint receives the user data from the gateway and stores a copy of the user data in a local memory.

Abstract: Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: A method is provided for fabricating a thin film oxide. The method include forming a first silicon layer, applying a second silicon layer overlying the first silicon layer, oxidizing the second silicon layer at a temperature of less than 400° C. using an inductively coupled plasma source, and forming a thin film oxide layer overlying the first silicon layer. In some cases, the thin film oxide layer overlies the oxidized second silicon layer and is formed by a high-density plasma enhanced chemical vapor deposition process and an inductively coupled plasma source at a temperature of less than 400° C. In some cases, the thin film oxide layer and the first silicon layer are incorporated into a thin film transistor and the thin film oxide layer has a fixed oxide charge density of 3×1011 per square centimeter.

Abstract: A method of forming a low-k inter-level insulator structure is provided comprising the steps of: providing a first metal layer; depositing a sacrificial insulator layer overlying the first metal layer; producing a second metal layer; removing the sacrificial insulator layer; and depositing a low-k inter-level insulator, whereby low-k material replaces the sacrificial insulator. An intermediate insulator layer structure is also provided comprising a sacrificial insulator layer overlying a low-k insulator layer, such that the sacrificial insulator layer may be subjected to processes, including CMP, which may be incompatible with low-k insulator materials.

Abstract: A method is provided to produce liquid crystal displays (LCDs) on polycrystalline films having a single predominant crystal orientation. A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize a region of the amorphous silicon to form a polycrystalline film with a preferred crystal orientation. In an embodiment of the method, the polycrystalline film is polished. A pixel region is formed over a portion of the substrate using either amorphous silicon or polycrystalline silicon. A circuit region is formed over the polycrystalline film.

Abstract: A method of forming a layer of high-&kgr; dielectric material in an integrated circuit includes preparing a silicon substrate; depositing a first layer of metal oxide using ALD with a metal nitrate precursor; depositing another layer of metal oxide using ALD with a metal chloride precursor; and completing the integrated circuit.

Abstract: A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.