Abstract: A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.

Abstract: A continuous paper web-moving mechanism has a supply roll on which the paper is wound and pulled from the supply roll by a drive roll that engages the paper on its surface by a pressure exerted against the paper at that point. In this preferred embodiment the pressure is exerted by a thermal printhead resiliently mounted to force the paper against the drive roll. A leaf spring is mounted at one end of the drive roll, bearing against the edge of the wound paper, providing a friction drag on the drive roll. Also, the drive roll is kept in a fixed lateral position by the force of the leaf spring, aiding in aligning the paper. The tension between the supply roll and the drive roll is such that the paper is stiffened, providing a contact with the surface of the drive roller in a tangential line.

Abstract: Monocrystalline gadolinium gallium garnet is prepared by the Czochralski growth process from a melt composed of the oxides of gadolinium and gallium. In order for this process to produce uniform crystal growth, the growing crystal must support a meniscus of liquid above the level of the surrounding melt. This meniscus is held up by the surface tension between the liquid and the growing crystal. It has been established that impurities in the meniscus region lower the surface tension of the liquid phase causing the meniscus to lose contact with the solid phase resulting in nonuniform crystal growth. By the addition of approximately 100 ppm of calcium into the melt, a counteracting effect is produced causing the meniscus to remain in contact with the growing crystal.

Abstract: A method for fabricating a magnetic memory film is disclosed wherein an epitaxial layer of magnetizable material is grown on the surface of a substrate which has been selectively implanted to damage portions of the crystalline surface. The resulting polycrystalline portion of the epitaxial layer grown on the damaged substrate surface is then selectively removed to leave the monocrystalline portions of the epitaxial layer.

Abstract: The present invention is embodied in a method of operating a dynamic random access memory (RAM) array having individual depletion mode metal-oxide-semiconductor (MOS) transistors as the memory cells. The cells can be programmed to two threshold states providing constant current sensing. Cell programming is by application of appropriate signals to the transistor gate electrode and source. Reading is accomplished by grounding the source and sensing current through the transistor. An intermediate voltage on the gate electrode prevents changes in the state of the cell.

Abstract: The liquid phase epitaxial growth of a magnetic garnet film is obtained by providing a circulating flux solution of the material, wherein spaced apart zones are maintained at different temperatures, above and below the saturation point; and by placing a preheated substrate in contact with the supersaturated zone, wherein a suitable growth temperature is maintained. This system avoids the prior need for heating and cooling the entire solution as a single, thermally uniform zone, and thereby achieves a substantial savings in time which permits at least a ten-fold increase in production rates, without increasing manpower or capital investment.

Abstract: Plastic housings for electronic components such as plastic cases for electronic wrist watches and calculators have their interior surfaces coated with a first layer of highly-conductive metal to provide static protection for the electronic circuitry contained in the housing, and a second metal layer overlaying the first layer to provide corrosion resistance for the first metal layer. In a preferred embodiment, the metal layers are formed by unique ion plating techniques.

Abstract: This invention deals with the fabrication of radiation emitting diodes having a small diameter shaped integral microlens formed by etching. Initially an oxide layer is deposited on the backside of the processed slice; then a ring pattern is opened in the oxide. An etch is used to form a ring groove with a mesa in the center. The center oxide dot over the mesa is removed and the etching continued to round off the edges of the mesa and to form a smooth shaped structure. Various shapes and diameters may be achieved with different ring dimensions and with different etch times.

Abstract: A dual gate FET has a first gate connected to receive an HF input signal and a second gate which is grounded to HF. The transistor output circuit is connected to a supply voltage terminal. A voltage divider comprising a resistor and a zener diode is connected between the supply voltage terminal and ground, the top of the voltage divider being connected to the second gate electrode. By varying the supply voltage, the amplifier gain can be adjusted. The supply voltage can be adjusted manually by a potentiometer. Alternatively, it can be adjusted automatically according to the strength of the HF input signal so that as the signal strength increases, the gain is reduced. The circuit is amenable to implementation using JFET, IGFET and MESFET transistors.

Abstract: A two-terminal optical sensor circuit comprising a light-emitting diode, phototransistor, amplifier, and current source electrically and optically coupled so as to approximate an ideal switch in one quadrant of its V-I characteristic. A remote object is detected when it moves into the optical path between the light source and sensor.

Abstract: A solid state keyboard comprised of a base module, a plurality of key members each having a plunger member comprised of a uniform mixture of a magnetic material such as barium ferrite and a binder such as nylon, and a respective plurality of improved Hall Effect Generators, provides a significant improvement in performance and cost effectiveness. Actuation of a key member moves its plunger member, which has a preselected magnetic field, relative to an improved Hall Effect Generator, in which offset voltage has been substantially eliminated. This movement exposes the generator to a change in the direction of the magnetic field, thus causing a corresponding change in the output voltage of the generator from a first predetermined voltage to a second predetermined voltage. A unique tripolar magnetic arrangement on the plunger member provides positive switching and better control of switching points.

Abstract: A temperature compensated, phase tolerant sense amplifier for use in a magnetic bubble memory system in which current is applied to the detector resistors only during a bubble detect operation.

Abstract: A high power microelectronic switching circuit is interfaced with a fiberoptic data link, whereby inductive or resistive loads up to 20 amperes are switched, with a forward voltage drop of less than one volt. An input signal of one-half milliwatt is passed to the gate of a V-MOS FET power device, which drives a PNP output transistor to switch a power supply to a circuit load.

Abstract: A Binary Coded Decimal (BCD) incrementing circuit and memory. The incrementing circuit has a small amount of delay associated with it so that it may be utilized as a stage of a shift register memory. The incrementing circuit includes an adder circuit, a sampling circuit and a detector circuit. The sampling circuit samples the most significant bit of a BCD digit when the least significant bit of the same digit is being outputted from the memory. The adder circuit adds one to the least significant bit in response to a control signal or one to the other bits in response to a carry condition in the adder and to a decimal carry signal. The detector circuit is coupled to the output of the memory, to the sampling circuit and to the control signal for generating the decimal carry signal and disabling the adder circuit when the control signal is present and the BCD digit being outputted is a decimal nine.

Abstract: In an N-channel MOS integrated circuit operating in response to a major-major clock having four phases, .phi.1, .phi.2, .phi.3 and .phi.4, each of which has one, but only one, other phase which does not overlap therewith, an improved gate is disclosed wherein a first one of said phases samples an input signal for retention via a capacitive device, a second one of said phases is gated according to the state of the sample retained via the capacitive device, and a third one of said phases enhances the retention of the capacitive device.

Abstract: A vibratory seismic energy source capable of generating significant energy over a broad frequency band. The vibrating baseplate and associated structure are designed to have minimum weight while still retaining sufficient structural integrity to permit the use of high actuator forces. This, coupled with a large reaction mass results in the generation of significant energy levels in the earth at high frequencies.

Abstract: A microelectronic integrated circuit having first and second levels of thin-film metallization separated by an insulation layer is provided with a system for electrical interconnections between metallization levels, at selected locations, without requiring extra spacing between metal paths, in either the first or second levels. Maximum circuit density is thereby permitted, with no restriction on the placement of interconnection vias. Circuit layout is greatly simplified because all metal paths have uniform widths and minimum spacings, achieved with the use of vias that are "oversized" in both the transverse and longitudinal directions. Consequently, it is required that second level metal differ in composition from first level metal, and be patterned with an etchant that does not attack first level metal.

Abstract: A method of communicating Digital Speech Data to a speech synthesis circuit. The data is compressed to on the order of 1000-1200 bits, per second for normal human speech. The speech synthesis circuit utilizes linear predictive coding techniques for producing high quality speech or other sounds.The data is preferably stored in a memory which is coupled to the speech synthesis circuit. The data has variable frame lengths; in the disclosed embodiment, four different frame lengths are described having frame lengths from four bits to forty-nine bits. The memory stores the variable frame length data and communicates the same to the speech synthesis circuit in response to certain control signals.

Abstract: A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

Abstract: A novel analog-to-digital converter is integrated on a semiconductor substrate utilizing I.sup.2 L techniques. The resulting converter, which utilizes dual slope integration to generate a digital signal, operates from a single low-voltage power supply and has few external components. The converter is suitable for integration with I.sup.2 L digital circuitry to provide a complete digital system, which operates in accordance with an analog input signal, on a single semiconductor chip.