Abstract: A disposable protective garment to to be worn over a worker's street or working clothing.

Abstract: An improved computer graphics memory architecture has a frame buffer and a Z buffer, each having a forward and reverse part, each of which is wide enough to handle two pixels of data. A data path is connected to the buffers so that in a 3-D application, a full pixel of both color and Z-value data is transported along the data path in a single I/O transaction. In a 2-D application, two pixels of data are transported along the data path in a single I/O transaction. In a preferred embodiment, both the frame and Z buffers are divided into two parts each wide enough to handle one pixel of data part. In 3-D applications, a data path is selectively connected to the buffers in a manner so that one pixel of color data and one pixel of Z-value data are simultaneously transported to the drawing processor during each I/O transaction. In this preferred embodiment, a first reversing switch such as a multiplexer circuit, is provided to reverse data that arrives from the buffer in reverse order.

Abstract: An antenna is provided including first and second strip resonant elements, a dielectric and a metal cover. The first strip resonant element has an F-shaped area that lies in a first plane. The second strip resonant element has an L-shaped area that lies in a second plane that is parallel to the first plane. The second strip at least partially underlies the first strip. The dielectric is positioned between the first and second strips. A metal cover is provided. Part of the metal cover is positioned perpendicularly to the first and second strips so as to provide electromagnetic shielding for the first and second strips.

Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports.

Abstract: An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree.

Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports.

Abstract: The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

Abstract: In a method of transferring a security element which is in the form of a laminate with a carrier foil and with a thermally activatable adhesive layer for connection to a substrate onto a document the adhesive layer is brought into contact with the substrate and locally heated by the supply of heat energy through the laminate. After the adhesive layer cools if necessary the carrier foil can be pulled off the substrate, in which case the carrier foil, at the locations adhering to the substrate, is detached from the rest of the laminate and the laminate tears along the boundary between the adhering and the non-adhering locations so that only the adhering locations of the laminate remain behind on the substrate. In particular a laser beam or an array of laser or light emitting diodes is suitable for the supply of heat energy. The laminate preferably has diffraction structures or layers producing optical interference effects.

Abstract: A process and device for the projection of image information before at least one eye (A1,A2) of a person having a visual impairment is disclosed. The visual impairment is caused by a deviation of the angular position of the optical axis of one eye (A2) in relation to the optical axis of the other eye (A1), i.e., cross-eyed. The process and/or device enables a cross-eyed person to see stereoscopically over a long period of time without any restriction in his/her field of vision. According to the process, one eye (A1) is selected as the leading eye, the movement of the leading eye (A1) is then detected, the position of the optical axis of that eye (A1) is determined from the detected movement, and image information is projected before the non-leading eye (A2) while taking an angular deviation into account. The projected image information is identical with the image information which the non-leading eye would perceive if its optical axis was in a position corresponding to the angular position of the leading eye.

Abstract: The invention comprises a method for producing electric sheets, in particular grain-oriented electric sheets, with an evenly well-adhering glass film and with improved magnetic properties, in which the hot rolled strip which is produced at first and is optionally annealed is cold-rolled up to an end thickness in one or several steps, thereafter an annealing separator is applied to the strip which is rolled up to the end thickness, and is dried, and therafter the cold strip thus coated is subjected to high-temperature annealing, with an important component of the annealing separator being a hydrous magnesium oxide (MgO) dispersion and the annealing separator being additionally provided with at least one additive. The characterizing feature of the invention is that a finely dispersed water-soluble sodium phosphate compound is used as at least one additive.

Abstract: The present invention relates to a method for dynamically allocating bandwidth to each encoder in an ensemble of video encoders whose output bit streams share a single communications channel. In accordance with the present invention, the channel bandwidth is allocated to the individual encoders in the ensemble in such a way that differences in a quality measure among the decoders are reduced. The quality measure includes a term that behaves like a peak-signal-to-noise ratio (PSNR) and a term that measures the "masking effect" in a video signal. The "masking effect" results because an encoded frame with a high visual complexity masks coding artifacts from the viewer when it is decoded and displayed.

Abstract: A low-voltage multipath-miller-zero-compensated operational amplifier is disclosed which includes a class AB front stage and a class AB back stage. The front stage has an inverted input, a non-inverted input, an inverted output, and a non-inverted output. The back stage has an output and input, which input is connected to the non-inverted output of the front stage. The output of the back stage is connected to the inverted output of the front stage. A capacitor is coupled in a feedback loop between the output and inverted input of the back stage. An operational amplifier in accordance with the present invention is particularly well-suited for use in switched-capacitor filters, continuous-time filters, microwave medical applications and general purpose amplification applications.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder wherein the rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the present invention relates to statistical multiplexing.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding.In particular, the present invention relates to statistical multiplexing.

Abstract: In a CMOS device uses a thin oxide film as a gate dielectric film, gate electrode plasma etching frequently induces gate dielectric damage. This invention discloses a process which can form a damage free gate dielectric even though there is plasma nonuniformity during gate electrode etching. In this invention, a thin polysilicon layer is formed on the gate dielectric (gate oxide) layer and a thin oxide layer (not gate oxide) is formed on the thin polysilicon layer. The thin oxide layer (not gate oxide) is then patterned and etched to expose portions of the thin polysilicon layer. A thick polysilicon layer used to form the gate electrode is subsequently deposited. The thick polysilicon layer contacts the exposed portion of the underlying thin polysilicon layer, but is otherwise separated from the thin polysilicon layer by the thin oxide. The thin polysilicon layer is patterned and etched using a plasma etching process. The thin oxide (not the gate oxide) acts as an etching stop.

Abstract: A character recognition system includes a character input device, such as a stylus and tablet or optical scanner, for receiving inputted characters, and a processor. The processor determines which of a number of model characters best matches the inputted character. To that end, the processor compares each inputted character to each of a plurality of classes into which the model characters are organized. Specifically, the processor extracts a feature value vector from the inputted character, and compares it to the mean feature value vector of each class. The processor recognizes the inputted character as the model character corresponding to the mean feature value vector which is closest to the feature value vector of the inputted character. The processor also constructs the database from multiple specimens of each model character. The processor organizes the specimens of each model character into multiple classes. The processor then determines the mean feature value vector of each class.

Abstract: A pipeline-able asynchronous logic circuit is provided that implements a subfunction of a logic function that is distributed into multiple sequential subfunctions. Each subsequent subfunction is applied to a result of an immediately preceding subfunction of the sequence. The asynchronous logic circuit has an output node and a differential logic circuit connected to the output node via a first path. The differential logic circuit applies a particular subfunction to an inputted signal to produce a result signal. The asynchronous logic circuit also has a sense amplifier that is connected to the output node via a second path which is distinct from the first path. The sense amplifier, in response to being enabled, amplifies the result signal produced by the differential logic circuit. The sense amplifier outputs the amplified result signal onto the output node.

Abstract: The invention is directed to a thin film transistor (TFT) wherein HF precleaning of a gate oxide layer is eliminated, thus avoiding surface degradation and maintaining the smoothness of the gate oxide layer. This results in a TFT that has low Ioff, low stand-by power, and high Ion/Ioff ratio. The invention forms a TFT by depositing a smooth surfaced TFT oxide layer over the TFT gate poly layer. The TFT gate poly layer includes a gate and a drain connection to the drain of a driver. No via hole is patterned over the TFT gate oxide before the TFT body film deposition. Therefore, no HF precleaning step is used. The TFT body layer is then deposited over the gate layer. Source and drain regions are formed in the TFT body layer. In order to connect to drain region of the TFT body layer with the drain connection in the TFT gate layer, a via is formed through the TFT drain and TFT oxide layer.

Abstract: A method and apparatus for reducing program clock reference (PCR) jitter in transport packets of a transport stream compliant with MPEG-2 or another suitable audio-video encoding standard. The PCRs from a given single program transport stream (SPTS) of a multi-program transport stream are processed in a phase-locked loop (PLL) to generate dejittered PCRs for that SPTS. The PLL for a given SPTS receives as inputs the PCRs from that SPTS and a cycle count for each PCR indicative of the number of asynchronous clock cycles counted since the previous PCR. The PLL generates a given dejittered PCR as a function of the previous dejittered PCR, the cycle count for the given PCR, and a clock frequency mismatch estimate for the given program clock. The clock frequency mismatch estimate is generated by filtering a sequence of jitter estimates, each corresponding to the difference between a previous PCR and its corresponding dejittered PCR.