Abstract: A semiconductor fabrication plasma property controller (100) for controlling physical properties of a fabrication process plasma medium (144) under the influence of electromagnetic gas discharge energy from a power source (38) comprises a control volume (130) disposed between the process plasma (144) and the electromagnetic gas discharge energy source (38). A control gas (128) flowing within the control volume prohibits a predetermined portion of the emitted electromagnetic energy from influencing the fabrication process plasma (144). The flow rate and/or pressure of the control gas (128) within control volume 130 is used to adjust the fraction of electromagnetic energy absorbed within process plasma (144) and to prohibit influence of a controlled fraction of the plasma-generating electromagnetic energy on the process gas, plasma stream (144). The control volume (130) absorbs the excess electromagnetic energy emitted by the power source (38).

Abstract: The invention relates to a method of measuring the contact angle of wetting liquids on a solid surface with which a high measuring accuracy and better reproduceability of the measurement results is achieved. The method resides in that a laser beam is directed onto the interface line between the liquid and the plane solid surface in such a manner that a first part of the laser beam is reflected by the solid surface and a second part by the liquid surface. The second partial beam is used as measuring beam by determining the angle (.delta.) made between the measuring beam and the solid surface, said angle being in a fixed geometrical relationship to the contact angle (r). The contact angles which can be determined very accurately with this measuring method provide information on wetting properties of materials, the exact knowledge of which is of great significance for example for semiconductor fabrication.

Abstract: Method and apparatus are disclosed for depositing a uniform layer of material, such as titanium dioxide, on the surface of an object, such as a silicon sphere of a solar array (7). Component gases are injected at predetermined rates into a heated reaction chamber (5) where they react. Because of the reaction rate and injection velocities of the gases, the reaction is substantially completed at a calculated location inside the reaction chamber (5). The object which is to receive the layer, such as the solar array (7), is placed at the calculated location in the reaction chamber (5). The platform (68) to which the solar array (7) is attached is simultaneously tilted and rotated such that all areas of the surface of the array (7) are uniformly exposed to the titanium dioxide reactant.

Abstract: An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ration of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio.

Abstract: A silicon-on-insulator MOS transistor (100) is disclosed which has contact regions on both the source (6) and drain (8) sides of the gate electrode (10) for (36,38) potentially making contact to the body node (12) from either side. Each contact region (36,38) is of the same conductivity type as the body node (12), (for example, a p-type region for an n-channel transistor), and may be formed by blocking all source/drain implants from the contact regions (36,38), so that the contact region (36,38) remains substantially with the same doping concentration as the of the body region (12). A mask is provided prior to silicidation so that the contact regions (36,38) on either side of the gate electrode (12) are not connected by silicide to the adjacent source/drain doped regions (6,8).

Abstract: A thermally and electrically conductive housing having a solid tip portion is shown mounting a heating element thermally and electrically coupled to the tip portion which in turn is electrically coupled to a switch mechanism mounted within the housing. The switch mechanism includes a thermostatic snap acting disc adapted to bias a movable electrical contact away from a stationary electrical contact at preselected temperatures. The housing is shown mounted in a carburetor of an automobile to contact energization of a honeycomb heater disposed in the carburetor, however; the device can be used in other locations where it is desired to maintain a body within a selected temperature range.

Abstract: A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

Abstract: A bipolar/CMOS integrated circuit uses an on-chip amplifier to provide an intermediate voltage supply (18) to two groups of small geometry CMOS circuits. Bipolar devices (24) may use a full five volts from the outside supply rails (12, 14).

Abstract: The disclosure relates to a method of forming samples of alloys of group II-VI compositions having minimum dislocations, comprising the steps of providing a sample of a group II-VI compound, providing an enclosed ampoule having the sample at one end portion thereof and a group II element of the compound at an end portion remote from the one end portion, heating the sample to a temperature in the range of 350 to the melting temperature of the compound for about one hour while maintaining the group II element at a temperature more than 200.degree. C. below the sample temperature, heating the group II element to a temperature from about 5.degree. to about 50.degree. C. below the temperature of the sample while maintaining the sample at a temperature in the range of 350.degree. to 650.degree. C. both of about 15 minutes to about 4 hours, and then stoichiometrically annealing the sample at a temperature below 325.degree. C.

Abstract: A video display system which can receive and display a number of different video signals having different formats utilizing a processor extract the image from a stream of digital signals to produce a digitized image to be displayed by a digital spatial light modulator.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectic is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.

Abstract: The deposition of zinc sulfide films (16) using dimethylzinc (46) and hydrogen sulfide (44) in a vacuum processor reactor (50) provides a low temperature process applicable for high volume production of infrared focal planes. These layers (16) of zinc sulfide are used as insulators and infrared anti-reflective coatings which are free of contamination relative to physical vapor deposited ZnS films. The zinc sulfide layers (16) are formed by evacuating a chamber (62) and mixing hydrogen sulfide gas (44) and dimethylzinc gas (46) at specific operating conditions until the desired ZnS film thickness is obtained. The rate of growth of the zinc sulfide (16) film is controlled by varying the temperature, pressure, and the relative flow rates of the hydrogen sulfide gas (44) and the dimethylzinc gas (46).

Abstract: A probe thermostat is shown having a single, stamped metal channel having a first coefficient of expansion coupled to a rod having a second, different, coefficient of expansion. An electrically insulating block is mounted on the channel which in turn cantilever mounts a pair of electrically conductive arms spaced one over the other with electrical contacts disposed on the arms in facing relation to one another. A molded plastic adjustment cam snaps into slots formed in the channel to adjust the position of the lower arm. A hinge formed in the channel and connected to the rod causes movement of the top arm as the temperature of the thermostat changes to cause the contacts to move into and out of engagement with each other.

Abstract: A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Shockley diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Shockley diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Shockley diode (22). The base (54) of the trigger transistor (24) is biased during normal operations iwth a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64).

Abstract: The described embodiments of the present invention provide structures and methods for fabricating the structures which provide compact contact from the surface of an integrated circuit to a buried layer formed in conjunction with a vertical gate extending from the buried layer to a doped layer at a surface of the integrated circuit. In one embodiment, trenches are simultaneously formed for providing the vertical gate and the contact to the buried layer. A thermal oxide layer is formed on the surface of the integrated circuit to provide an insulating layer on the surfaces of both the contact trench and the gate trench. A first layer of in situ doped polycrystalline silicon is deposited on the surface of the integrated circuit. The thickness of this polycrystalline silicon layer is chosen so as to not fill the gate and contact trenches. A masking layer is then provided to protect the gate trench and expose the contact trench.

Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

Abstract: A carrier-susceptor for use in a continuous chemical vapor deposition reactor system serves as a carrier, cover and heat susceptor for a semiconductor wafer being processes through the reactor system.

Abstract: An infrared tracker for tracking a carrier in clutter comprises a pyrotechnically heated emitter, a beam concentrator, and a blanking means all of which are mounted on the carrier, and a command link, a thermal detector, a display signal storage means, a display, and a comparator all of which are located remotely to the carrier, said command link operative to provide an emitter start-up signal and a blanking command signal, said emitter and blanking means operative in response to the command signals sent to the carrier when there is clutter present that might be confused with the carrier, respectively, to actuate the emitter and blanking means, said display storage means operative to store a first video frame of the carrier while the emitter is blanked out, and said comparator for ocmparing the first video frame without the emitter to a subsequent video frame including the emitter to distinguish between the clutter is being substantially canceled.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: This is a vertical MOSFET device with low gate to drain overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, and a gate electrode 36 surrounding the vertical pillar not substantially extending into the highly doped drain contact region 30.