Abstract: An optical-disc writer writes extrinsic data to an optical disc. Extrinsic data can be written as (i) embedded marks (e.g., pits and lands) located outside the conventional readable area of a disc and/or (ii) alternative marks, such as surface marks located on a surface of the disc. In an optical-disc player having a disc-reading subsystem and a read controller, the disc-reading subsystem reads and relays the extrinsic data to the read controller, which controls the operations of the player based on the extrinsic data. For example, the writer prints extrinsic data, e.g., a barcode, on the surface of a software installation disc. The disc is inserted in the player and installation is commenced. The read controller instructs the disc-reading subsystem to read the extrinsic information. If the read controller determines that the extrinsic data was successfully read, then installation proceeds; otherwise, installation is halted.

Abstract: An optical coherent detector that employs an interleave-chirped arrayed waveguide grating (AWG). The AWG has a periodic chirp pattern that enables the AWG to function as an optical 90-degree hybrid. If the AWG is implemented using a birefringent material, then the AWG can also function as a polarization demultiplexer. In one embodiment, the AWG is designed to simultaneously function as a wavelength demultiplexer, a polarization demultiplexer for each wavelength-division-multiplexed (WDM) signal component, and a 90-degree hybrid for each polarization-division-multiplexed component of each WDM signal component.

Abstract: An improved speakerphone for a cellular telephone, portable telephone handset, or the like. In one embodiment, a receiver provides an audio signal, and a first phase-shifter phase-shifts the audio signal by a first phase-shift amount. A second phase-shifter phase-shifts the audio signal by a second phase-shift amount and drives a loudspeaker. A processor sets the first phase-shift amount to each one of a plurality of phase-shift amounts and determines a corresponding average-to-peak ratio value of the first phase-shifted audio signal. The processor then selects one of the plurality of phase-shift amounts having a corresponding average-to-peak ratio value that meets at least one criteria (e.g., the largest one of the average-to-peak ratio values), and then sets the second phase-shift amount to be the same as the selected phase-shift amount. This enhances the perceived loudness of sound from loudspeaker.

Abstract: In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N?1 operating mode (that serializes (N?1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.

Abstract: In one embodiment, a demodulator demodulates a multi-carrier modulated signal having two pilot tones. The demodulator calculates a first phase angle for the first pilot tone and a second phase angle for the second pilot tone based on the time-domain multi-carrier modulated signal. A timing-frequency offset estimate is calculated using the first and second phase angles. Further, a fine carrier-frequency offset estimate is calculated for each pilot tone based on the corresponding phase angle and the timing-frequency offset estimate. Each fine carrier-frequency offset estimate is combined with a coarse estimate and weighted. The weighted estimates are then combined. In further embodiments, the timing-frequency offset estimate is weighted and combined with a weighted timing-frequency offset estimate generated using a cyclic prefix. In yet further embodiments, the weighted carrier-frequency offset estimates are combined with a weighted carrier-frequency offset estimate generated using a cyclic prefix.

Abstract: This invention relates generally to footwear with a shoe sole, including at least one insertable midsole orthotic. The insertable midsole orthotic is removably inserted within the shoe upper, the sides of which hold it in position. The shoe sole includes a concavely rounded side or underneath portion, which may be formed in part by the insertable midsole orthotic. The insertable midsole orthotic may extend the length of the shoe sole or may form only a part of the shoe sole and can incorporate cushioning or structural compartments or components. The insertable midsole orthotic permits replacement of midsole material which has degraded or has worn out in order to maintain optimal characteristics of the shoe sole and allows customization for the individual wearer to provide tailored cushioning or support characteristics for the purpose of orthopedic, podiatric, corrective, prescriptive, therapeutic and/or prosthetic purposes.

Abstract: In one embodiment, a method for correlating log entries in a log file to the line numbers of formatted-string output functions in source code, where the formatted-string output functions contain instructions to generate the log entries in the log file. The method includes locating the formatted-string output functions in the source code, where each formatted-string output function contains a format string. Each format string is processed to generate a corresponding regular expression to match log entries outputted by the corresponding formatted-string output function. Each regular expression is associated with the line number of the corresponding formatted-string output function. The resultant list of regular expressions and corresponding line numbers is processed with the log file, where log entries in the log file are modified to indicate the line numbers associated with matching regular expressions.

Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.

Abstract: In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

Abstract: A variable-stride multi-pattern matching apparatus segments patterns and input streams into variable-size blocks according to a modified winnowing algorithm. The variable-stride pattern segments are used to determine the block-symbol alphabet for a variable-stride discrete finite automaton (VS-DFA) that is used for detecting the patterns in the input streams. Applications include network-intrusion detection and protection systems, genome matching, and forensics. The modification of the winnowing algorithm includes using special hash values to determine the position of delimiters of the patterns and input streams. The delimiters mark the beginnings and ends of the segments. In various embodiments, the patterns are segmented into head, core, and tail blocks. The approach provides for memory, memory-bandwidth, and processor-cycle efficient, deterministic, high-speed, line-rate pattern matching.

Abstract: A routing protocol, according to one embodiment of which a first station of a wireless network monitors its outgoing transmissions corresponding to a traffic flow for occurrence of multi-tier signals and for ability to achieve a specified minimum transmission rate. Based on the monitoring, the first station may transmit an outgoing solicitation message that identifies the monitored traffic flow as a candidate for rerouting. Upon receipt of the solicitation message, a second station of the wireless network evaluates whether rerouting of the monitored traffic flow through the second station is capable of increasing data throughput for that traffic flow without decreasing data throughputs for other traffic flows presently handled by the second station. Based on this evaluation, the second station may transmit to the first station an offer to reroute the monitored traffic flow. The first station, in turn, evaluates this offer, e.g.

Abstract: In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.

Abstract: In one embodiment, a bracket for mounting a rod to a surface has a surface-mounting portion and a rod-attachment portion. The surface-mounting portion provides an interface between the bracket and the surface, and attaches to the surface using suitable fasteners such as screws or nails. The rod-attachment portion has an aperture formed therein that accepts a threaded fastener used to attach a finial to the end of the rod. The aperture has a dimension that is smaller than a diameter of the rod, and at least as large as a diameter of the fastener. In one exemplary method of using the bracket, the fastener, attached to the finial, is fed through the aperture into a socket in the rod. The finial is then rotated thereby coupling the finial to the rod until the rod-attachment portion is secured between the rod and the finial.

Abstract: A representative digital circuit of the invention has an on-chip, non-volatile memory, to which chip-specific speed-binning data that characterize performance of the digital circuit are written during production testing. During normal operation, the power controller that controls power-supply signals applied to the digital circuit reads the speed-binning data from the on-chip memory for use as input parameters for dynamic supply-voltage scaling, dynamic clock scaling, and/or adaptive power control that optimize (e.g., minimize) power consumption in the digital circuit. Advantageously over the prior art, the accuracy and efficiency of dynamic and/or adaptive power control arc improved because the chip-specific speed-binning data enable the power controller to better customize the power-management algorithm for the given digital circuit.

Abstract: An image projector having one or more broadband lasers designed to reduce the appearance of speckle in the projected image via wavelength diversification. In one embodiment, a broadband laser has an active optical element and a nonlinear optical element, both located inside a laser cavity. The broadband laser generates an output spectrum characterized by a spectral spread of about 10 nm and having a plurality of spectral lines corresponding to different spatial modes of the cavity. Different individual spectral lines effectively produce independent speckle configurations, which become intensity-superimposed in the projected image, thereby causing a corresponding speckle-contrast reduction.

Abstract: Forming a thin film acoustic device by patterning a layer of non-conducting material on a first side of a substrate to expose a portion of the first substrate side; depositing layers of conducting material on the layer of non-conducting material and the exposed portion of the first substrate side; depositing a layer of piezoelectric material on the layers of conducting material; depositing and patterning additional layers of material on the layer of piezoelectric material to form a first device electrode; depositing and patterning a masking layer on a second side of the substrate to expose a portion of the second substrate side; etching away the exposed substrate portion to expose the patterned layer of non-conducting material and a portion of the layers of conducting material; and etching away the exposed portion of the layers of conducting material to form a second device electrode.

Abstract: In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.

Abstract: A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and/or functional blocks that are only partially rendered in gates.

Abstract: Petri net models, of systems, communication protocols, and software programs, which include place objects, transition objects, arcs, and initial markings, may be used for testing and verification. To reduce computations, a new unfolding process is performed on the net models. Two or more candidate buffer place interfaces are selected from the input net model. The input net is subdivided with a preliminary cut to form two subnets, wherein the preliminary cut passes through suitable candidate buffer place interfaces, objects of each of the subnets other than the suitable candidate buffer place interfaces are reachable from at least one initial marking, and the subnets do not include a mix of initial and non-initial marking places. Each of the two subnets are unfolded and then joined to form an unfolded net that is behaviorally equivalent to original input net model. The unfolded net is then stored in a storage unit.