Abstract: In particular, a system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a small FIFO memory and skips unused bus cycles to avoid the requirement for memory speed to match the processor bus speed. A time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data. Triggers are established to capture only those processor words that appear on the bus and which are also of interest. The remaining words are compacted by removing parts of the words that are not of interest from those words that remain in the queue based on the trigger criteria.

Abstract: Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. The application of a code for 128 bit memories is applied to a 20 bit directory store to improve reliability of the directory store memory of the computer system. The code uses ×4 bit DRAM devices organized in a code word of 20 data bit words and 12 check bits. These 12 check bits provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 20 bit word, with single bit correction across the word as well. Each device can be though of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word.

Abstract: In a computer system a system of exchanging tokens for queue banks is created that permits a requester to directly specify which queue bank is wanted. Only the desired queue bank is withdrawn from a queue bank repository to accomplish this and no sorting or FIFO handling of queue banks is needed. The system uses a schema similar to a coat check room, where the requester is given a token when the requestor wants to deposit a queue bank into the queue bank repository. The queue bank repository returns the queue bank when the token is returned by the requester. In its most efficient form, two machine-level instructions handle the entire operation, a withdraw instruction and a deposit instruction.

Abstract: Secure access to internal data resources is facilitated through a gateway CGI on an internet visible computer system with an internet visible web server configured by rules to forward calls to the gateway CGI. The gateway CGI packages information from the call to send by secure socket connection to a server-like access control program on a secure host system which can reconstitute the call if authenticated and/or validated and serve the request, returning the sought after data or resource through an encrypted channel if desired. Variations for high throughput environments and operation with application program session controllers are described.

Abstract: Electronics manufacturers, particularly ones building large scale computer systems, have a need to describe test vectors for third party manufacturers in a low level language description that does not reveal the circuit design to the third party but allows for the third party to build and test the systems, not just with static tests based on BSDL and netlist files, but dynamic tests as well. A conversion process for taking a high level language circuitry description and producing test vectors useable for translation into actual test vectors for testing board-level components of the large scale computer systems is described.

Abstract: Serpentine trace patterns are used to add length to traces for matching delays to groups of signals on separate transmission pathways on circuit boards. By providing reverse coupling by patterning the traces in concentric fashion, this invention enables closer spacing between adjacent trace segments of the serpentine pattern.

Abstract: In order to implement alternative pathways and procedures for handling a separate set of software locks, an arrangement of circuits is described. These circuits allow for generating and handling specific requests for communal software locks without additional software development through pathways and procedures separate from ordinary lock handling operations. A side door communications pathway is set up to handle the communal locks separately from the ordinary data transfer pathways through which ordinary software locks get handled. Supporting and controller circuits handle the locking and unlocking process as well as communicating results of lock requests back to requesters.

Abstract: Building and testing complex electronic products especially large scale computer systems are handled with control remaining with the owner of the design while a contract manufacturer does the basic manufacturing processes and testing. Nearly all levels of testing are accomplished without sharing high level descriptions of the end product or its features by providing only low level files for test functions. Testing is accomplished without sharing the high level code descriptive of the system design so confidential information is retained. Testing using the low level data is made sufficient to identify what parts need repair despite the lack of high-level information transfer.

Abstract: A method for efficiently saving data to tape, preferably within the ANSI X3.27 standard format sends signals to the tape drive to allow the tape drive to buffer the required tape marks, which the standard requires. Although the standard presumed these would be required for synchronization and would be written when produced, we do not adhere to that thinking. Instead we synchronize only at the logical end of the application constructed file, or at the end of the tape in one embodiment, saving time in writing through avoiding stop-start activities of the tape drive, thus allowing newer tape drives to take advantage of the features of the ANSI X3.27 standard. We also provide an embodiment, which allows for non-ANSI standard (i.e., unlabeled) tapes to be used.

Abstract: Control over access by individuals to a group of high security facilities and zones within such facilities is accomplished with use of biometric readers at each access door as well as a quick ID reading device that is not required to contain biometric information. Enrollment at a secure facility where biometrics are maintained for each individual establishes a multipart data file for each individual, each part of which may be accessed by different actors in the system. The individuals allowed security to various facilities can only be in a single facility at a given time and also control their own schedule.

Abstract: A method is provided for developing a computer-based dialogue interface for an automated or computerized system using input device technology. The dialogue interface is disposed between the automated system and an end user, with the dialogue interface receiving input from the end user and providing output to the end user in response to the input. In an illustrative embodiment, the method comprises the following steps. A system designer(s) defines a plurality of requirements applicable to the dialogue interface. The dialogue interface is then designed to meet these requirements. The automated system is simulated with at least a first person, and the end user is simulated with at least a second person. The dialogue interface is evaluated by facilitating an interaction between the first and the second persons through the dialogue interface. Based on the interaction between the first and the second persons, the dialogue interface is evaluated.

Abstract: A matrix of single input OR-gates correspond to respective codes to be assigned to strings. The inputs of the OR-gates are coupled to respective outputs of a code decoder that is responsive to a fetched input code. The locations of a character and level table, respectively accessible by the code decoder outputs, store the extension characters of extended strings recorded in the decompressor. Outputs of OR-gates are selectively coupled to code decoder outputs through a matrix switch to sequentially couple OR-gate outputs to OR-gate inputs so that the characters of a string corresponding to the input code are provided from accessed locations of the table. An update extended string is recorded by coupling the output of the OR-gate corresponding to the next assignable code to the code decoder output corresponding to the previously received code. The first character of the string corresponding to the current code is stored in the table location accessible by the next assignable code.

Abstract: Multi-processor computer systems with multiple levels of cache memories are given an alternate pathway for handling highly contended-for locks. These are called communal locks. The alternate pathway allows for alternate processing schemas that do not impede the performance of the overall system as is otherwise the case in such computer systems where contended-for locks bounce back and forth between contending caches, crimping storage bus bandwidth and system performance. The alternative pathway is not used for ordinary (non communal software lock) data and instruction transfers.

Abstract: Methods and apparatus that enable a transport protocol executing on a first computer system to be utilized by applications executing on a second computer system which is directly interconnected and closely coupled to the first computer system. An interconnection couples an input/output (I/O) subsystem of the first computer system to an I/O subsystem of the second computer system and provides a path over which data can be transmitted between the first and second computer systems independent of a network interface card, and an interconnection messaging system executing on the first and second computer systems provides general purpose transport interfaces between said first and second computer systems.

Abstract: A code evaluation algorithm is used to determine optimal cache parameters. In evaluating the code, the algorithm uses a set of code characteristics the presence of which, or the degree of presence of which, impact the proper selection of cache parameters. Once the code characteristics have been selected, the algorithm uses boolean truth state tables or fuzzy logic membership set definitions to specify whether and when each code characteristic is true or false (i.e., present or absent) for a given set of code instructions. Programs are classified as having the following characteristics: 1) arithmetic intensive; 2) logic/decision intensive; 3) reference intensive; and/or 4) array/vector/table processing. To evaluate the code, the degree of presence or absence of these characteristics is described in logical fashion, using fuzzy logic.

Abstract: A system is provided for releasable engagement between two structures. The system includes a stud extending outwardly from one of the structures along an axis. The system also includes a resilient member positioned adjacent a surface of the other one of the structures. The resilient member is configured to expand radially outwardly to permit passage of the stud, yet the surface of the structure contacting the outer surface of the resilient member prevents movement of the outer surface radially outwardly. The resilient member is configured to engage the stud for releasable engagement, thereby providing releasable engagement between the structures.

Abstract: A computer-aided design (CAD) tool is used to create a preliminary design of a mulit-layered printed circuit board, comprising a layout of electrical components on a main region of a printed circuit board and a routing of signal traces among the lectical components within the main region. An extended region is then added to the design on the CAD tool that comprises a layout of selected debug connectors on the extended region and at least one additional signal layer. Traces connecting the debug connectors to selected vias of the main region of the printed circuit board are then routed on the added signal layer only. A prototype board is then created and tested. Once testing is complete, the extended region and the at least one additional layer are removed from the design in the CAD tool without disturbing the layout of components and routing of signal traces on the main region of the printed circuit board.

Abstract: A matrix of AND-gates correspond to respective codes to be assigned to strings. The outputs of the AND-gates are selectively coupled to prefix code inputs of the AND-gates through a prefix code matrix switch. A plurality of characters from the input stream are fetched into an input character buffer and applied through respective character decoders and selectively through a character matrix switch to character inputs of the AND-gates. An AND-gate-corresponding to a code assigned to a string that is the longest match to the plurality of fetched characters is thereby enabled. Update extended strings are recorded in the AND-gates, an extended string comprising a longest matching string extended by the data character following the longest matching string. A virtual level is assigned to an AND-gate indicative of the number of characters of the string recorded thereby, the virtual level being one greater than the level that had been assigned to the AND-gate corresponding to the longest match.

Abstract: An inventive protocol for communicating between a management processor and host processors allows for the cooperative management of resources among host processors within a partition and also among a set of partitions in a computer system, wherein each partition may function under an instantiation of an operating system with a group of host processors. The protocol employs a message passing system using mailbox pairs in fixed but moveable or relocatable locations within the computer system shared memory. The messages share a format having specific codes or descriptors that act as codes for coordination of message interpretation. These codes include at least a validity flag and a sequence enumerator, and in a response message of a request/response message pair, a status indicator. Additionally, routing codes and function codes and code modifiers may be provided. Specific implementation details and messages are described to enable the smooth functioning of complex multiprocessor systems.

Abstract: Radar coverage maps having blockage, coverage and clutter features available for ease of interpretation are provided using terrain data to establish such features in data sets. The data sets provide a basis for the modified display. Multiple tilts of the radar scan may be represented. Multiple radar zones may be overlapped to provide a mosaic of a region showing areas of no coverage despite overlap.