Abstract: Circuitry and methods for improved amplifiers with large bandwidth and constant gain-are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.

Abstract: Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.

Abstract: A circuit that provides the root-mean-square (RMS) value of an input signal and that detects and independently recovers from an output fault condition is provided. The circuit includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit provides a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to normal operating mode and provides a DC output signal proportional to the RMS value of an AC input signal.

Abstract: A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

Abstract: Driver circuitry with a tuned output impedance is provided. Tuning is provided by an isolation circuit and matching network coupled to an output of the driver circuit. The isolation circuit isolates the capacitance associated portions of the driver circuit thereby reducing overall output capacitance. The matching network substantially compensates for reactive impedances associated with other portions of the driver circuit. These tuning circuits allow the driver circuit overcome intrinsic reactance and exhibit a substantially resistive output impedance characteristic.

Abstract: A slope compensation circuit that provides slope compensation signals for switching voltage regulators is provided. The slope compensation circuit includes a feedback circuit, a control circuit, and a slope signal generator circuit. The feedback circuit generates a feedback signal that is indicative of both input and output voltages. The control circuit acts as a voltage controlled resistor that varies its resistance based on the feedback signal in order to control the slope signal generator circuit so that an optimum amount of slope compensation is provided.

Abstract: A circuit that provides the root-mean-square (RMS) value of an input signal and that detects and independently recovers from an output fault condition is provided. The circuit includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit provides a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to normal operating mode and provides a DC output signal proportional to the RMS value of an AC input signal.

Abstract: Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.

Abstract: A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

Abstract: A photodetector circuit that operates a reduced power levels is provided. The photodetector circuit preferably includes a control circuit that alternates between an active mode and a standby mode. During an active mode, information regarding the relative strength of a light signal is acquired and reported. However, during a standby mode, portions of the photodetector are disabled or turned off so that no information regarding a light signal is acquired or reported and overall power consumption is reduced.

Abstract: A pallet for carrying dynamo-electric machine component workpieces of different dimensions is provided with first and second support members, at least one of which is movably mounted on the pallet so that the distance between the support members can be adjusted to accommodate a wide range of differently dimensioned workpieces. The pallet may include an aperture which allows a removal device to pass through and remove a workpiece from, or deposit a workpiece to the pallet. Each movable support member is releasably locked so that a user may unlock and adjust the support members to a desired position.

Abstract: An oversampling delta-sigma analog-to-digital converter suitable for single-cycle operation is provide. In a preferred embodiment of the present invention, only one multiply-accumulate processor is present in the digital filtering stage for decimating the output sequence R(I). A system controller produces precisely timed modulator enable (EnM) and digital filter enable (EnF) signals for coordinating activation of certain circuit elements and for managing power consumption of the system.

Abstract: This invention provides apparatus and methods for causing a fluorescent lamp drive circuit to provide a continuous drive signal over a first (high) range of lamp intensity, and a pulse width modulated (PWM) drive signal over a second (low) range of lamp intensity, with a smooth transition between continuous and PWM drive that is unnoticeable to the user. This invention also provides fluorescent lamp circuits that include lamp intensity control circuitry, fluorescent lamp drive circuitry and a fluorescent lamp, the lamp intensity control circuitry providing control signals that cause the fluorescent lamp drive circuit to provide a continuous drive signal over a first (high) range of lamp intensity, and a PWM drive signal over a second (low) range of lamp intensity, with a smooth transition between continuous and PWM drive that is unnoticeable to the user.

Abstract: An electronic circuit tester (e.g., for testing integrated circuit wafers or packaged integrated circuits) is provided. The tester is preferably based on a relatively inexpensive computer system such as a personal computer and includes at least one high-precision clock circuit that is programmable with respect to frequency and number of clock pulses. The high-precision clock circuit is connectable to the circuit being tested to permit certain timing-critical tests to be performed, even though a large number of other data channels in the tester are controlled by a relatively low speed clock circuit. The tester also includes analog circuitry that can be programmed to provide various analog signals suitable for performing parametric testing on an electronic device under test.

Abstract: The design of logic for implementation in programmable logic array integrated circuit devices is facilitated by allowing various characteristics of modules in the logic design to be parameterized. Specific values for a parameter can be “inherited” by a logic module from other logic higher in the hierarchy of the logic design. Default values for parameters can also be provided. The user can design his or her own parameterized modules, and logic designs can be recursive, meaning that a logic module can make use of other instances of itself.