Abstract: Microwave circuit layout structure is disclosed for a diode mixer bridge. The circuit layout structure is compact and symmetric, and enables short orthogonal equal length leads from a diode ring quad mixer bridge. The configuration also affords equal path lengths through the diodes to provide precise 180.degree. phase differential image frequency cancellation. The structure also affords precise and consistent mounting of the mixer bridge, to further improve performance.

Abstract: A retaining device is provided for preventing removal of a fiber optic connector module from a card cage when a mating fiber optic cable connector is attached to the module. A pivoted release lever on the module has a hook automatically engaging a slot in the card cage upon insertion, and is manually operable to a release position only when the mating fiber optic cable connector is disconnected from the module.

Abstract: In a digital transmission system, a loop-timing technique is provided for a channel bank which demultiplexes a high speed data stream into a plurality of lower rate channels, and which multiplexes a plurality of lower rate channels to a high speed data stream. Loop-timing is provided without elastic buffers by deriving stuff requests from stuff bits in the received high speed data stream, extracting a high speed clock signal from the received data stream, and applying the stuff requests and the high speed clock signal directly to the high speed multiplexer for providing stuff bits in the transmitted high speed data stream and for clocking the transmitted high speed data stream.

Abstract: A two terminal transfer linearization circuit is provided for linearizing the AGC voltage of an AGC amplifier by providing a selectively controllable nonlinear current-vs-voltage response curve with adjustable curvature. A pair of end terminals have a first circuit branch therebetween forming a voltage divider for supplying base drive voltage to a transistor in a second parallel circuit branch between the end terminals. A third parallel resistorless circuit branch is provided through a second transistor having base drive voltage across a third resistor in the second circuit branch. As the voltage across the end terminals increases, the current through the first transistor increases and this current increases the base drive voltage to the second transistor to turn on the latter in nonlinear manner. The shape and curvature of the resultant current-vs-voltage response curve is selectively adjusted by variable resistors in the first and second circuit branches.

Abstract: A simplified digital NRZ data phase detector is provided with a minimum number of components and with an expanded measuring interval to enable the use of slower speed components. In a phase locked loop application, a first input gate, such as a flip-flop, responds to NRZ data, and a second input gate responds to clock pulses and the output of the first gate. Variable and fixed width correction signals are derived directly from the outputs of the first and second gates, respectively, within a measuring interval initiated by a data transition and terminated by a clock transition. The difference in duration between the directly derived variable and fixed pulses provides phase indication.

Abstract: Microwave circuit layout structure is disclosed for a diode quad mixer frequency converter with separate, isolated sections, each supplied by a respective half of dual balun port structure. The circuit layout structure is compact and symmetric, and enables coplanar diode connection.

Abstract: A time division demultiplexer is provided which reassigns clock positions to the various channels in a serial data stream such that different data bit positions may be assigned to a channel. This enables each channel to be independent. A single channel can access any data bit position in the serial data stream, and several or all the channels can access the same data bit position.

Abstract: A muldem (100) has a monitor (101) for testing data path failures through the muldem (100) by comparing the latter's input and output. The muldem (100) has normally on-line data paths (103, 104) therethrough, and includes normally off-line standby data protective switching means (108, 109) providing alternate data paths. The monitor (101) tests on-line and off-line data paths before and after protective switching to the standby alternate data path, to guard against silent failures and to prevent switching to an inoperative path. In an auto-revert mode, a latched display continues to display an alarm, after the malfunction is corrected and the muldem has switched from standby to main.

Abstract: A muldem (100) includes a transmit multiplexer section (103, 104) combining a variety of low speed and intermediate speed digital data inputs into a single high speed data output. A monitor (101) is provided for testing data path failures through the muldem (100) by comparing the latter's input and output. The monitor (101) includes comparing means (806, FIGS. 13a and b) which accepts both low and intermediate speed data from the inputs for comparison against the high speed data from the output.

Abstract: A muldem (100) has a monitor (101) for testing data path failures and standby data protective switching means (108, 109) providing an alternate data path in the event of a malfunction. The system accepts up to fifty-six standard low speed T1 LS lines (1.544 Mb/s), up to fourteen standard intermediate speed T2 lines (6.312 Mb/s), or any combination of T1 and T2 lines to generate to standard HS lines (44.736 Mb/s). The T1 circuitry is replaceably interchangeable with the T2 circuitry.

Abstract: A muldem (100) includes a transmit multiplexer section (103, 104) combining a variety of low speed and intermediate speed data inputs into a single high speed data output and a demultiplexer section providing low and intermediate speed outputs from a high speed input. A monitor tests data paths of the muldem for detection of malfunctions and initiates protective switching through a standby alternate data path around the low or intermediate speed circuits and, independently, around the high speed circuits.

Abstract: A low frequency diode mixer is provided in combination with simple, compact transformer circuitry. A four diode mixer interconnects three dual transformers. The mixer has a pair of separate, isolated two diode sections commonly servicing the first transformer and separately servicing the other two transformers.

Abstract: A microwave frequency converter is provided with a diode mixer bridge having a balanced port connected to a dual balun. The dual balun is provided by two pairs of balanced secondary conductors juxtaposed a common primary conductor, each pair contributing to the field between balanced conductors leading to the mixer bridge. The dual balun and microstrip circuit layout enable a wider gap to be used between the balanced conductors to the bridge, which enables manufacturably cost efficient implementation.

Abstract: A -3 dB microwave quadrature coupler is provided on a single layer dielectric substrate and employs only two conductor coupling lines and a relatively wide, cost efficiently manufacturable coupling gap. The substrate is suspended within a mounting case providing a minimum spacing above and below the substrate. The ground plane is on the bottom of the substrate. Microstrip conductor ports are on the top of the substrate and are connected to a pair of parallel spaced coplanar conductor lines on top of the substrate juxtaposed a cut-out region of the ground plane therebelow. The coplanar conductor lines are balanced and coupled to each other, not to the ground plane nor to the mounting case. The coupler is compact, with a reduced length of .lambda./8. The coupler is amenable to implementation on inexpensive low dielectric constant substrate material, still with a relatively wide coupling gap.

Abstract: A mechanical bandpass filter with acoustic sensing is disclosed, including a particularly advantageous implementation enabled thereby in the detection of automobile engine knock. A pair of cantilever beam resonators of different resonant frequencies are connected at their nodes to a single in-phase velocity source which is directly acoustically driven and which has an infinite stiffness relative to the flexure mode resonators. The resonators have piezoelectric transducers of opposite polarity electrically coupled in such a relation as to define upper and lower attenuation stopbands due to signal cancellation and to define a passband frequency, due to signal reinforcement. The passband corresponds to the frequency range between and around the resonant frequencies of the two resonators. The invention provides a wide bandwidth without spurious response mode effects.

Abstract: A digital phase detector is provided for NRZ data phase detection. In a phase locked loop application, the detector generates a variable duration pulse between a data transition and a positive transition of the recovered clock, and generates a fixed duration pulse between the positive clock transition and the next negative clock transition. The difference in duration between the variable and fixed pulses provides phase indication.

Abstract: A digital sampling phase detector is provided for NRZ data phase detection and is particularly suited for applications with long sequences of no data activity. In a phase locked loop application, phase error circuitry detects the phase difference between data transitions and clock transitions of the recovered clock, and outputs phase error signals corresponding to various durations between designated transitions. Sampling switching circuitry responds to a data transition to initiate a measuring interval by forcing the output of the phase error circuitry to a low impedance follower mode to permit sampling, and responds to a designated clock transition to terminate the measuring interval by forcing the output to a high impedance state. The sampling switching circuitry prevents the sampled signal level from drifting during a non-measuring interval, and the reduction of drift significantly reduces jitter in the recovered clock. The sampling function is provided in combination in a high speed ECL phase detector.

Abstract: A VCO (Voltage Controlled Oscillator) is provided with a full set of tuning voltages from a reduced number of reference voltage sources, such as potentiometers. Logic controlled switch means delivers any of the reference voltages individually or predetermined combinations thereof as the tuning voltages to the VCO. A reference voltage source potentiometer is provided for each of the odd numbered tuning voltages, and a piecewise linear approximation is provided for the intermediate even numbered tuning voltages by generating the average of two adjacent odd voltages.

Abstract: An energy conserving drive circuit is provided for switched mode power converters having a transformer with primary current controlled by a main power switch whose conduction is in turn controlled by a pulse width modulator. Transformer leakage inductance energy is applied to drive the pulse width modulator and the main power switch in a run mode after start-up. The drive circuit includes an improved non-dissipative snubber network which supplies the drive power for the main power switch and which also disables a start-up circuit.

Abstract: A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of gates which maintain the set and reset states of the first flip-flop for two consecutive clock pulse edges between set and reset transitions to provide symmetrical output pulses from the first flip-flop of frequency 1/3F with a substantially 50% duty cycle.