Abstract: An amplifier suitable for carrier current line driver applications is shown. It includes a triangle wave to sine wave shaper circuit and an automatic level control. It incorporates a line surge arrestor circuit that is active even when the transmitting capability is disabled. The circuit is shown in an integrated circuit form, the output of which is capable of being boosted by off-chip components.

Abstract: In an integrated circuit, back to back zener diodes are connected between circuit pads and each zener diode shunts a resistor in a series string. When a suitable pulse is applied to the pair, the back biased diode will be selectively shorted. Thus, the pulse polarity will determine which diode will short and which resistor will be bypassed. In this manner a pair of pads can be used to selectively short out either one or both of a pair of diodes and a trimming section can be created using only half of the pads required in the case where each zener is contacted separately. The invention is directed to a structure in which the forward biased zener diode is protected so that only the reverse biased diode shorts out when the pulse is applied.

Abstract: A pair of transistors, connected as a differential amplifier, is operated so that the transistors run at different current densities. A voltage divider is coupled across a pair of circuit terminals so that a portion of the terminal voltage is coupled to and used to differentially bias the transistors. An amplifier, responsive to the transistors differential output, and coupled to the divider, is used to vary the terminal voltage to force the differential output to zero. The transistor bias voltage thus generated has a positive temperature coefficient of voltage. A forward biased diode, which has a negative temperature coefficient of voltage, is also incorporated into the divider. When the terminal voltage is made equal to the semiconductor bandgap, the two temperature sensitive terms cancel to compensate the reference voltage.

Abstract: A programmable fuse circuit has a fusable polysilicon element programmable in response to an "illegal" condition on existing pins of an integrated circuit. This programmable fuse circuit is incorporated in a programmable partial memory circuit, a reconfigurable format memory circuit, and a chip select circuit.

Abstract: A programming pulse generating circuit, suitable for use on an electrically alterable read-only semiconductor memory, that decouples from the high voltage supply when in a standby condition so as to not draw current from the supply. Alternative voltage supply connections are effected by depletion mode devices.

Abstract: A circuit for clearing selected bytes in a semiconductor electrically alterable memory in which the ground lines for any one column of bytes is isolatable from the ground lines for other columns, all the outputs for the bytes are urged toward a non-clearing condition, and the outputs for only the selected byte are used to introduce a clearing signal that dominates the non-clearing condition.

Abstract: A circuit to restrain the rise time of a programming pulse generated in an electrically alterable read-only semiconductor memory in which excessively sudden changes in the pulse are capacitively coupled, through active devices that can be built on the chip, to a grounding switch device so as to periodically drain away the control signal used to create the pulse.

Abstract: A power transistor design that eliminates thermally initiated secondary breakdown in fast, double-diffused transistors is described. The power dissipation capability is made independent of collector voltage, avoiding safe area restrictions below 0.9 BV.sub.CBO.

Abstract: A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor and an NPN bipolar transistor. The method includes applying an erase voltage, e.g. +20 volts, to each of the Y sense lines while maintaining each of the X sense lines at this erase voltage and each of the X write lines at ground and applying the erase voltage to each of the source lines such that each of the PMOS transistors assumes a relatively negative threshold state. The method includes applying a write voltage e.g., +20 volts, to selected X write lines while maintaining unselected X write and selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage e.g., +10 volts, which is less than the write voltage, and maintaining each of the X sense lines at an intermediate voltage e.g.

Abstract: A wide bandwidth amplifier is shown along with a muting circuit. The output shift between normal operation and mute is kept very small. The amplifier is useful in video disk and audio signal reproduction.

Abstract: A heat molded optical fiber interconnect molds one end of a plastic optical fiber around light emitting surfaces of a light source such as a light emitting diode to provide a highly efficient optical and mechanical coupling between the optical fiber and the light source. In one preferred embodiment an efficient interconnect for coupling large diameter optical fibers has a converging lens heat molded in the other end of the plastic optical fiber to efficiently couple light to another optical fiber or receiver.

Abstract: In a digital tester for evaluating electronic components, a local memory unit for each data channel in the tester is loaded with test vector information only in the locations of the memory relating to transitions that take place in the operation of the data channel. In addition, a transition bit is stored in each memory location to signify whether the vector information in that location represents valid transition data. The transition bit is used to control the reading of information from the memory into a register that controls the flow of information in the data channel, so that only the valid transition vectors are fed into data channel control circuitry. This procedure substantially reduces the amount of data that must be loaded into the memory, and hence reduces the total time necessary to thoroughly test a circuit.

Abstract: A method of annealing an ion implanted semiconductor device using an antireflective dielectric coating on the device for maximizing the coupling of photon radiation into the device. An IGFET device made in accordance with the method, is shown.

Abstract: A trigger circuit with hysteresis is created by driving a latch circuit set and reset terminals through a pair of emitter driven complementary transistors the bases of which are returned to a reference potential V.sub.REF. The hysteresis is set by the V.sub.BE potentials of the complementary transistors. When the input emitters are driven more than one V.sub.BE above V.sub.REF, one transistor will conduct and set the latch. When the input falls below one V.sub.BE below V.sub.REF, the other transistor will conduct and reset the latch. A digital filter is created by coupling a capacitor across the trigger circuit input and digitally driving the capacitor through a transconductance amplifier.

Abstract: A CMOS integrated circuit is made compatible with TTL input signals. A regulator operates the CMOS gates in an array at a voltage that is slightly lower than the supply. The regulator sense circuit is made responsive to an operating gate and to a TTL bias reference. Accordingly, the regulator will compensate for changes in ambient conditions and manufacturing variations so that the gate array devices will reliably respond to TTL level switching signals.

Abstract: A linear differential amplifier is fabricated in CMOS and combined with digital control so that an analog input signal can be converted to a selected output polarity. When the amplifier output is coupled directly to the inverting input the noninverting input provides a unity gain voltage follower configuration. To create a unity gain signal inverter, a matched pair of resistors is employed. One resistor is coupled between the amplifier output and the inverting input while the other is coupled between the analog signal input and the inverting input. In operation digital control is employed in switching between the two configurations. The sense of the differential amplifier is reversed when switching between configurations thereby to provide a substantial reduction of the effect of offset potential. To fully compensate the offset potential, a capacitor is periodically coupled across the amplifier input to charge it to the offset potential.

Abstract: A plurality of differential amplifier stages in cascaded in a directly coupled configuration to provide substantial signal gain. The first few stages are cascode coupled to a plural input differential signal combiner which has a single differential output that feeds a full wave differential peak detector. The peak detector therefore has an output that rises as a log function of the signal input. This signal-related voltage is then fed to a differential dc amplifier which in turn drives a meter that indicates the log of the input signal strength. The amplifier cascade is stabilized by a dc feedback loop.

Abstract: A pad for connecting electrical chips in microelectronic circuits includes a passive protective layer overlapping the edge thereof and a bump built up on the connecting pad that had a dimension of the base that is less than that of the pad to prevent the bump from overlapping the edges of the pad and damaging or cracking the underlying structure of the chip during thermocompression bonding of leads to the bump.

Abstract: A discrete, precut strip, lead frame plating system wherein each strip is loaded onto a linked chain, located against plating masks, contacted electrically, plated, dried, and unloaded from the chain in successive sequential fashion.

Abstract: To cut a strip of metal into exact lengths, rollers are brought into contact with the strip and turned by an accurate motor until a pin can be mechanically inserted into a hole in the strip to effect final alignment. If the pin does not successfully enter the hole, a detector halts the system.