Patents Represented by Attorney, Agent or Law Firm Michael R. Casey
  • Match register with duplicate decoders
    Patent number: 5798656
    Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: August 25, 1998
    Assignee: Xilinx, Inc.
    Inventor: Thomas A. Kean