Abstract: A multimedia system comprises an application program title that also comprises a multiplatform interpreter. The application program contains both the application described in a scripting language and the multi-media data. A platform subsystem interacts with the application program title and accesses the application program and interpreter. It executes the application program under control of user input means. Also a user display and an audio subsystem are controlled by the application program. The application program is based on an instruction set that is interpreted by the processing means, using the multiplatform interpreter. The platform is an instance of a prespecified abstract machine with predefined instruction set, data type set, and resource facilities according to quantitative minimum requirements.

Abstract: The invention provides a clock sensor that can be operated at very low current and power. This sensor can also detect an input clock signal with a very small amplitude to detect the presence of clock inputs. According to one embodiment of the invention, a clock sensor comprises an input circuit configured to receive an input clock signal; a biasing circuit configured to receive the input clock signal and to provide biasing voltages; and a switching circuit configured to receive the biasing voltage and in response to the input clock signal, to provide a switching signal for switching an output circuit to generate an output clock signal. The input clock signal may have a small amplitude and the output clock signal has a full amplitude.

Abstract: A way-determination scheme for an n-way associative cache is provided that is based on the entirety of the line address of a requested data item, thereby eliminating the possibility of a mis-identification of the way that contains the requested data item. A limited number of line addresses, and their assigned ways, are stored in a Way Determination Table. If a requested data address corresponds to one of these line addresses, the assigned way is provided; if not, a ‘null’ response is provided, indicating that the way is not known for this data address. If an assigned way is provided, the way corresponding to this assigned way is accessed, with the assurance that the accessed way contains the requested data item. If a ‘null’ response is provided, the n-ways are accessed to determine whether the requested data line is in the cache, as in a conventional n-way associative cache.

Abstract: A transmitter has a quadrature modulator that provides a modulated signal at a first frequency. The transmitter has a phase locked loop of which a voltage controlled oscillator is coupled between a phase comparator of the phase locked loop and further has a transmit power amplifier in a transmit signal path of the transmitter. The phase locked loop further has a down-converter in a feedback path from an output of the transmit power amplifier and a feedback input of the phase comparator. The transmitter further has an amplitude restoration arrangement that restores amplitude information contained in a feedback signal provided by the down-converter and in the quadrature modulated signal. In operation, the phase locked loop replicates at a carrier frequency angle information contained in the quadrature modulated signal, and the amplitude restoration arrangement controls the gain of the transmit power amplifier such that input signals at the phase comparator substantially are equal.

Abstract: An output driver circuit that can be used to determine whether a repeater buffer is the only device driving a bus low. According to the invention, the current through the output driver circuit of the repeater buffer is compared with a reference current. If that current is greater than the reference current, then the output driver circuit (i.e., the repeater buffer) is the only output driving the bus low. On the other hand, if that current is less than the reference current, then the output driver circuit (and thus the repeater buffer) is not the only device driving the bus low. This information can be used in an I2C repeater to determine the proper response of the repeater and prevent a latch condition.

Abstract: The available amount of storage space of a fixed HDD on a CE device is adjustable via a data network. The consumer can upgrade the device via a third party service that remotely control's the HDD's settings.

Abstract: A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a “universal” memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.

Abstract: A cellular radio communication system has a number of cells covered by base stations communicating with mobile communication devices. The mobile communication device performs an idle handoff method. In the idle handoff method, the communication mobile device receives paging messages from a first base station, and initiates idle handoff from the first base station to a second base station if it is established that no other, critical idle-mode process with the first base station is being performed.

Abstract: The present invention provides an improved measuring circuit for measuring a current of an inductor with minimum losses and errors. According to one embodiment of the invention, the measuring circuit comprises an op-amp, a RC network connected in a feedback loop of the op-amp, and a scaling resistor connected in series to one of the input terminals of the op-amp. By setting the RC constant of the RC network to be equal to the ratio of the inductor value over its internal resistance value, the inductor current can be derived independent of the frequencies of AC signals.

Abstract: A memory access architecture and technique employs multiple independent buffers that are configured to store items from memory sequentially. The memory is logically partitioned, and each independent buffer is associated with a corresponding memory partition. The partitioning is cyclically sequential, based on the total number of buffers, K, and the size of the buffers, N. The first N memory locations are allocated to the first partition; the next N memory locations to the second partition; and so on until the Kth partition. The next N memory locations, after the Kth partition, are allocated to the first partition; the next N locations are allocated to the second partition; and so on. When an item is accessed from memory, the buffer corresponding to the item's memory location is loaded from memory, and a prefetch of the next sequential partition commences to load the next buffer.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: A multiport device is configured to recognize each active segment on a bus, and to selectively propagate signals within the device depending upon whether the segment is active. Optimal signal propagation is achieved by invoking the control of the propagation of signals only after a first active-transition on the bus. Initial transitions are propagated unconditionally, to minimize propagation delay, and subsequent signal propagations are conditionally controlled, to avoid latch-up. A latch is associated with each port. The latch is set each time the port is actively driven by a device on that port. The latch is reset when all the devices are in the quiescent state, or when another port remains active after the currently active port becomes inactive. The state of each port's latch controls the propagation of internally generated signals to the port. If the latch is set, internally generated signals are not propagated to the port, thereby preventing latch-up.

Abstract: The present invention provides a random sequence generator for generating an output signal having random values. The generator comprises a plurality of cells inter-connected to one another such that each cell receives, as an input, an output from each cell connected thereto and generates a cell output based on a current value of the cell output and each cell output received. The plurality of cells include k subsets, each subset including n cells. A pre-selected cell from each of the k subsets generates an output and the output of the k pre-selected cells is provided as the output signal of the generator. In a specific embodiment, each of the cells is a linear cellular automaton, with k being an instruction width and k*n being an instruction length. The invention is particularly suitable for internal self-testing of a microcontroller in a smart card. This eliminates the need for external test contacts and thus prevents potential break-ins through the external contacts.

Abstract: A digital radio device having a quadrature demodulator that does not suffer from substantial amplitude roll-off at the relevant operating range. Such a device is obtained by a phase shifting network in a quadrature branch of the demodulator having a series arrangement of a resistor and an capacitor coupled to an inductor coupled to ground. A junction between the series arrangement and the inductor forms the output of the quadrature branch. Alternative embodiments are provided. The demodulator avoids asymmetric digital signal distortion which can have deteriorating effects, in particular to GFSK-signals or &pgr;/4-DQPSK signals, or the like, and further noise shift of data which is of particular importance in low [S/N]-systems such as paging systems.

Abstract: A cellular communication system has a number of cells covered by radio base stations communicating with communication device. The communication devices have a master timer for internally timing the communication devices relative to a timing of the cellular communication system. The master timer of a communication device is initially synchronized to a timing reference of a radio base station that provides the currently best communication link. Upon initial synchronization, the communication device determines and stores a first channel profile of received multi-path signals relative to the initial synchronization, and then enters a sleep mode. In the sleep mode a timing reference that controls the master timer is switched off. From the sleep mode, the communication device enters a receive mode and switches on its timing reference.

Abstract: A method for networking processing sub-systems is provided in the present disclosure. The method enables sharing of a resource between a plurality of information processing sub-systems wherein at least one sub-system is a PC and at least one sub-system is an upgrade. The method enables the PC to be informed about access to an upgrade. The method enables the upgrade to broadcast a message with an IP address and a port number. The method enables the PC to set up, in response to the message, a proxy client for communicating with a port of the upgrade indicated by the port number. The method enables the upgrade to set up a proxy server to handle a request from the proxy client for access to a second resource. The method further enables registering with the PC of a second interface to the second resource for access to the second resource from the PC.

Abstract: According to a particular example application, the present invention is embodied in the form of first and second current-steering sections arranged to steer a differential current input signal. Each of the first and second current-steering sections is current driven via differential current paths. The first current-steering section configured and arranged to source current and thereby drive the second current-steering section. Another aspect of the invention employs stacked Gilbert cells, as described above, to form a variable gain amplifier (“VGA”) circuit that achieves a large dynamic range, a wide frequency response and improved linearity, while consuming relatively low amounts of power.

Abstract: A method for detecting and correcting incorrect hand position of a computer user performing the steps of: a) receiving a word having a plurality of characters from an input device; b) comparing the received word with a plurality of entries contained in a dictionary word list; c) generating a shifted word by shifting at least one of the plurality of characters to a new character if the received word is not found in the dictionary word list; d) comparing the shifted word with the plurality of entries contained in the dictionary word list; e) correcting for the incorrect hand position of the computer user if the shifted word is contained in the dictionary word list; and f) performing again steps C through E if the shifted word is not found in the dictionary word list of step C.

Abstract: A method is described of controlling a communication system using a continuous FDD channel. Each time segment of the channel is divided into a predetermined number of sub-segments. For a first set of time segments, the communication signal data for the respective time segment is repeated in all sub-segments, and for a second set of time segments, null periods are provided in one or more of the sub-segments during which the communication signal from the first station to the second station is interrupted. The communication signal data is transmitted during the remaining sub-segments of the second set. This approach enables a slotted transmission mode to be established in a CDMA FDD system, without the need to adapt the spreading ratio of the CDMA system.

Abstract: An on/off control circuit is provided that controls the application of power to a device. The effectiveness of the on/off control circuit is optimized with regard to cost, power consumption, component life, and utility. An R-C circuit is used to provide a time-delayed turn-on, and turn-off, of the device being controlled, accompanied by a latch that retains the on/off state and controls the coupling of a power source to the device being controlled. The latch is configured as a data flip-flop (DFF) with a clocking signal that is controlled by the time-delayed switch input. The flip-flop has an inverted output signal as its input, thereby providing a toggled on/off operation. The latch also includes an independent reset input, thereby allowing an independent turn-off operation by power management controllers within the device being controlled. In the quiescent state, the preferred embodiment consumes less than half a microWatt of power.