Abstract: A DC-offset correction circuit (I1, Q1) for a low-IF or zero-IF receiver, comprises a DC-offset control loop (O1, O2) embodied by: a summing device (9-1, 9-2) having a signal path input (10-1, 10-2), a DC control input (11-1, 11-2), and a summing output (12-1, 12-2); and an offset determining means (15-1, 15-2) coupled between the summing output (12-1, 12-2) and the DC control input of the summing device (9-1, 9-2). The DC-offset correction circuit (I1, Q1) further comprises a DC blocking circuit (17-1, 17-2) coupled to the summing output (12-1, 12-2) of the summing device (9-1, 9-2) and having a DC blocking output (18-1, 18-2) for providing an offset corrected output signal. The DC-offset control loop (O1, O2) and the DC blocking circuit (17-1, 17-2) advantageously interact in correcting DC offset.

Abstract: The present invention relates to a compiling method and system for generating a sequence of program instructions for use in a processing architecture with architecture resources executing instructions from a corresponding instruction set. A retargetable compiler is used to generate a code using at least two instruction sets in the same processing architecture. One instruction set for a compact code and one for a parallel high performance code. The compact instruction set (Compact Instruction Format) covers a subset (RF11, ALU1, L/S1, BU1) of the architecture, whereas the complete instruction set covers the entire architecture (RF1, UC1, UC2, RF2, UC3, UC4, RF3, UC5, UC6, RF4, UC7). By using the at least two instruction sets of different sizes, the compiler is able to reduce the processed average code length, since fewer bits are needed in the compact code to encode operations and registers.

Abstract: A circuit arrangement for a resistor of high linearity that can be produced in integrated technology and be controlled by the current (Io1, Io2), which circuit arrangement is constructed from two pairs of transistors comprising transistors (T1 . . . T4) of the same junction type connected as diodes. Each pair of transistors (T1, T2 and T3, T4) has a common point of connection (D, E) that connects together the anodes of one pair of diodes and the cathodes of the other pair. The point of connection (D) of the first pair of transistors (T1, T2) is situated on their collector lines and thus connects the anodes and forms the infeed point for a first control current source (Io1). The point of connection (E) of the second pair of transistors connects the cathodes and is thus situated on their emitter lines and forms the infeed point for a second control current source (Io2).

Abstract: Data transmission from a data carrier (D) to a station (1) normally takes place by load modulation of a non-modulated carrier signal (CS) by means of an auxiliary carrier signal (SCS1), test means provided in the station then test the correct data transmission and, upon detection of disturbed data transmission, a change over is made to an other transmission mode in which data transmission takes place from the data carrier (D) to the station (1) by means of load modulation of the non-modulated carrier signal (CS) by means of at least one other auxiliary carrier signal (SCS2).

Abstract: A battery and circuitry for monitoring state of charge of the battery are housed in a single housing. A display may be provided for displaying an indication of the state of charge, and a communication circuit may be provided for communicating electrical signals representing the state of charge to the exterior of the housing. Preferably, the battery module additionally includes a switch device for connecting the battery to terminals external to the housing and control circuitry responsive to the monitoring circuitry for causing the battery to be connected to and disconnected from the terminals. The control circuitry operates in accordance with thresholds to prevent deep discharge and overcharge.

Abstract: The state of charge of a cell that has flexible packaging and that expands and contracts with variations in state of charge is determined by measuring changes in thickness of the cell. The invention is particularly applicable to cells having a flat geometry. A battery having a state-of-charge indicator includes at least one battery cell free to expand and contract with variations in state of charge of the battery cell and a device for measuring expansion or contraction of the battery cell, a resulting measurement indicating the state of charge of the battery cell. By measuring expansion or contraction of the battery the state of charge of a battery may be readily detected. The measurement may be directly displayed so as to be visually observable, or a signal containing measurement information may be sent to a remote location to be displayed or used for control purposes.