Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

Abstract: A protection circuit for electrically programmable non-volatile memory cells includes at least one first control circuit connected between first and second voltage references and having at least an input terminal and an output terminal wherein the output terminal delivers a reading/programming voltage signal to the cells. The protection circuit also includes at least one second control circuit having a first input terminal for receiving an enabling control signal, a second input terminal for receiving a Power-on-Reset signal, and an output terminal for supplying a control signal to the first input terminal of the first control circuit. The protection circuit further includes a disabling circuit connected between the first and the second voltage reference and having an output terminal connected to the first input terminal of the first control circuit. The disabling circuit comprises at least one redundant memory element connected between a translated voltage reference and the second voltage reference.

Abstract: The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage and an amplifier output stage connected serially together to receive an input signal on at least one input terminal of the amplifier and generate an amplified signal on an output terminal of the amplifier. Provided between the input and output stages is an intermediate node which is connected to a compensation block to receive a frequency-variable compensation signal therefrom. The compensation block is coupled with its input to the input terminal of the amplifier The compensation block is connected to receive at least the feedback signal. Preferably, the compensation signal is variable as a function of a gain value which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value.

Abstract: The present invention addresses the limitations of prior art ALLNODE switches by including dual priority, adaptive, path seeking, and flash-flood functionalities in a single ALLNODE switch. The switch of the present invention further includes a selection device responsive to a selection signal for enabling the selection of the mode of switch operation from any one of the foregoing functionalities. The selection signal is applied to the switch in a number of different ways including: the transmission of a command over the data path interface to the switch; the transmission of a command over special purpose serial or parallel control lines; or via hardwiring. Thus, the selection of functionality for the switch is capable of being made in either a dynamic or static fashion. The present invention further comprises two new high performance networks utilizing the selectable function ALLNODE switch.

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator.The method of this invention provides for:the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; andthe utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function.

Abstract: A circuit for limitation of maximum current delivered by a power transistor comprises: a network for detection of the current delivered by the power transistor which generates a first electrical signal; a reference network for generating a reference current proportional to a resistor and self-limited, provided by means of a current generator circuit and a limiting circuit with current mirror; and an operational amplifier which compares the first electrical signal with the reference current and which tends to inhibit the power transistor if the current delivered exceeds a certain threshold value.

Abstract: A tester having as an interconnect structure a pair of resilient, elastomeric, vise-like interconnect grips having conductive tracings thereon. This interconnect structure provides electrical conduction between the conductive tabs of an adapter card under test and the tester.

Abstract: A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

Abstract: An electronic module is provided including a chip bonded to a flexible laminate, and an apparatus for establishing coplanarity of a surface of the module, the apparatus comprising (1) a stiffener having a recessed portion for receiving the chip mounted to the flexible laminate, the recessed portion including a first planar surface and a second planar surface with the two planar surfaces being substantially parallel to each other, and (2) an adhesive bond line along the second planar surface for attaching the flexible laminate to the stiffener, the adhesive bond line including a plurality of spacers embedded within the adhesive bond line.

Abstract: A dual priority switching apparatus for making input port to output port connections on a requested basis quickly and dynamically, in a standard mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously. The apparatus permits multiple broadcasts to be queued at the individual switching apparatus which resolves the broadcast contention on a synchronous priority driven basis that permits one broadcast to follow the other at the earliest possible moment and the quickest possible speed. The apparatus permits multiple multi-cast operations to occur simultaneously within the network. The multi-cast function permits subsets of nodes assigned to the same tasks to communicate among themselves without involving other nodes that are not in its own subset. Hardware circuitry detects and corrects deadlock conditions in the multi-stage network.

Abstract: A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.

Abstract: A multi-stage architecture for providing a single switching component in multiplicity to create a single network capable of performing a multiplicity of functions. One function of the disclosed network is to circumvent the traditional blocking problems in multi-stage networks by implementing ALTERNATE PATHS between devices within the same network. This permits a non-blocked path between 2 devices to be found by rearrangeability--the act of trying or searching different alternate paths until a non-blocked connection is established. A second network function permits a special high priority mode of transfer which will guarantee that the connection will be made to an idle device as rapidly as possible.