Abstract: A handheld computer has a generally rectangular housing on a front side wall of which a display screen is operatively mounted. A row of toggle switches is also mounted on the front housing side wall, adjacent the display screen, the toggle switches being operatively connected to the computer circuitry within the housing. The toggle switches are manually depressible switch members having first and second non-momentary positions. The housing may be manually grasped in two perpendicular use orientations in each of which the user may reach and operate the toggle switches to control the operation of the computer. One of the toggle switches is operative, via the internal computer circuitry, to selectively rotate, through an angle of 90 degrees, the orientation of data generated on the screen so that in either of the first and second housing use orientations the screen data is in an upright viewing orientation relative to the user of the computer.

Abstract: A power supply including a detection and switch system for sensing either a uni-plane or a split-plane device connected to a socket and for providing one or two supply voltages, respectively. In one embodiment, a dual output regulator includes first and second regulators with corresponding first and second feedback circuits and comparators for regulating first and second outputs, respectively. A switch circuit connects the second feedback circuit to the comparator of the second regulator in split-plane mode for providing the second output. However, the switch circuit connects the first feedback circuit to the comparator of the second regulator in uni-plane mode where the two outputs are coupled together by a uni-plane device, so that the two outputs are regulated at the same level. A detection circuit monitors the output signals and controls the switch circuit depending upon whether a uni-plane or split-plane device is detected.

Abstract: A rechargeable battery pack including a microcontroller connected to a voltage measuring circuit and a current measuring circuit for measuring, respectively, the voltage across and the current flowing from a battery. Upon each expiration of a predefined time period during each discharge cycle of the battery, the microcontroller computes the product of the voltage, the current, and the length of the time period, thereby computing the energy expended by the battery over each period of time. An energy variable stored in a nonvolatile memory device associated with the microcontroller for representing the total amount of energy output by the battery over the life thereof is incremented by the computed energy. In one embodiment, a temperature sensing circuit measures the temperature of the battery and the instantaneous energy is adjusted by a temperature factor associated by the measured temperature before being used to increment the value of the energy variable.

Abstract: A digital computer system has an error correction code (ECC) syndrome encoder for generating initial ECC syndromes from digital words input to the system which are received together with their corresponding ECC syndromes, in the system receiving circuitry. The system has an ECC syndrome re-encoder for generating second ECC syndromes from the digital words as they are removed from the receiving circuitry. A comparison circuit then compares the originally encoded syndrome with the re-encoded syndrome as it is being generated, to detect whether there is a difference and therefore an error in the digital word or an error in the syndrome. The comparison circuit is integrated into and is a part of the ECC re-encoder.

Abstract: A method and apparatus for identifying option modules or expansion devices coupled to an expansion bus using time domain methods. According to the present invention, each expansion device includes logic circuitry that asserts an identification signal a preset time duration after a host reset signal is pulsed. A unique preset time duration or time constant is designated for each expansion device, and the host computer identifies each expansion device by the length or duration of the identification signal. In the preferred embodiment, during the power-on sequence the computer system asserts a reset signal pulse to the identification logic in each respective expansion device which directs the expansion device to assert its identifying signal. The host computer determines the length of time between assertion of the reset signal pulse and assertion of the identification signal and uses this information to determine the type of expansion device.

Abstract: A synchronous regulator circuit including a transformer having a secondary inductor magnetically coupled to a primary inductor, where the secondary inductor is coupled to control a synchronous power switch. The secondary inductor operates to drive the synchronous power switch using self-regeneration during a flux reversal phase of each cycle. A timing circuit or simple pulse width modulation circuit (PWM) turns on the primary switch and turns off the synchronous switch during a power phase of each cycle, and then turns off the primary switch during the flux reversal phase of each cycle. The flux reversal of the secondary inductor drives the synchronous switch on, thereby achieving synchronous operation without an expensive dual output PWM. The present invention is illustrated using both a buck and a boost topology. A third switch is preferably used to clamp the synchronous switch off during the power phase.

Abstract: A store queue is provided that forms an interface between a primary bus and a secondary bus and which temporarily stores data to be written via a memory or I/O channel to a peripheral device. The store queue allows partial writes executed on the primary bus to be combined within a common word storage cell of an internal FIFO buffer regardless of whether the consecutive partial writes result in an invalid byte combination. If the data being transferred does not constitute an invalid byte combination, the store queue executes a single write cycle on the secondary bus. If the data contained by the word memory cell constitutes an invalid byte combination, the store queue executes two or more partial writes on the secondary bus to transfer the data in the order it was received. The store queue includes a byte order tracking circuit, such as an accumulation counter, for tracking the order in which the bytes are written from the primary bus.

Abstract: A combined multiprocessor interrupt controller and interprocessor communication mechanism includes a system bus, an input/output bridge element coupled to the system bus, and a system controller coupled to the system bus. The input/output bridge element includes circuitry for receiving interrupt requests, for obtaining processor-associated vectors, and for packaging obtained processor-associated vectors into interprocessor communication messages. The system controller includes circuitry for receiving and decoding interprocessor communication messages, and for providing processor-associated vectors to the associated processor.

Abstract: A digital computer system includes a central processor unit (CPU) and an optional co-processor unit, both connected to a local bus. The co-processor unit, when installed, fits into a socket having pins, the pins being connected to communicate with the CPU through the local bus. A presence-detect circuit is connected to the local bus and receives a signal indicating the presence of the co-processor unit in the socket. Logic circuitry receives the output signal from the presence-detect circuit and provides a READY-- signal in either the presence or absence of the co-processor unit.

Abstract: A digital computer system includes an interface for routing data which permits the transfer of data between mismatched devices. The computer system comprises a processor, memory and an interconnecting data bus, all configured to handle data units of a first data width. Also connected to the data bus is at least one I/O device configured to handle data units of a second data width. By adjusting the width of the data being transferred to match the width of the receiving device or bus, data may be transferred between devices of differing width. To adjust the width, control means are provided which modify the route along which data bytes are transferred based upon the width of the transferring and receiving devices and the direction of transfer are provided.

Abstract: To facilitate the registered connection between a laminated multi chip module and an associated multi-tiered circuit board, spaced series of vias are formed transversely through the circuit board and module substrates between their opposite first and second sides. Gold plated BGA leads, offset from the module substrate vias, are formed on the first module substrate side on multi-layer plating structures disposed thereon and extending along the module via interior side surfaces. A spaced series of relatively shallow, circularly cross-sectioned socket areas, offset from the circuit board vias, are also formed on the first side of the circuit board. The sockets have diameters slightly larger that those of the generally ball-shaped BGA leads of the multi chip module, and are positioned on the same centerline pattern as the leads.

Abstract: A CD ROM server comprises a CD ROM drive and an array of hard disk drives. Means are provided for copying data from the CD ROM drive to the array of hard disk drives, and for deleting data from the array of hard disk drives, upon receipt of copy and delete requests, respectively, from a host computer system. Means are provided for the host computer to read data from the array of hard disk drives in the CD ROM format that the data had been stored in on the CD ROM. Means are also available to implement RAID technology with the array of hard disk drives for data reconstruction, striping, and redundancy. Means may be provided for the host computer to communicate directly with any SCSI devices connected to the server.

Abstract: An apparatus and method for a computer system that selectively disables expansion peripheral interface devices so that they do not interfere with diagnostic testing of related computer system peripheral interface devices. The present invention selectively disables the peripheral interface devices by control of the clock signals thereto. The clock signals may be selectively controlled by means of a software test program that may also be used to automate the diagnostic testing of the computer system. In addition, the computer system may be remotely tested and diagnosed because the present invention makes it unnecessary for the physical removal of devices that may cause false signal responses during the diagnostic tests.

Abstract: A macro-system which includes at least one portable computer and at least one stationary computer. The stationary computer includes a docking bay into which the portable computer is physically inserted whenever the user has returned with it to his primary work area. This docking station includes contact probes which automatically make contact to a small number of contacts on the back of the portable computer whenever it is stuffed into the docking station. The portable computer preferably includes soft power switch logic, so that an activation signal, received when the portable computer is docked, can be used to wake up the portable computer and bring it up active in a slave operating mode. Appropriate software routines can then be triggered to maintain file coherency.

Abstract: A battery charger including a control system for controlling a linear pass element to maintain relatively constant power dissipation of the linear pass element. In one embodiment, the charge current and the voltage across the linear pass element are provided to a constant dissipation amplifier, which increases the charge current as the voltage of the linear pass element decreases due to charging of the battery. The charge current is increased in such a manner to maintain the power dissipation of the linear pass element to a relatively constant level. In another embodiment, the battery voltage is provided to the amplifier, which increases charge current in response to rising battery voltage to maintain constant power dissipation of the linear pass element. The latter embodiment is in recognition that the voltage across the linear pass element is inversely proportional to the voltage across the linear pass element.

Abstract: A fault tolerant disk array subsystem is provided that includes a plurality of data drives for storing real data and a parity drive for storing redundant data. Each data drive is associated with a dedicated write-through cache unit and the parity drive is associated with a dedicated write-back cache unit. An array scheduler schedules read and write operations to access the data drives and includes a parity control unit for updating parity information when new data is written to one of the data drives. Since a write-back caching technique is used to store updated parity information, the write latency of the parity drive does not limit the write-throughput of the disk array subsystem. Furthermore, since a non-volatile memory unit is provided to store the addresses of any dirty parity information within the write-back cache unit, parity information can be reconstructed in the event of a power failure.

Abstract: An embedded core laminate including a conductive reference plane interposed between two insulation layers, and further interposed between two conductive layers. The assembly is laminated using standard temperature and pressure laminating procedures. Holes for interconnect vias are preferably drilled into the reference plane before laminating. The resulting embedded core laminate has three conductive layers with relatively uniform separation, insuring improved impedance control on each PCB (printed circuit board). Since uniform separation is maintained from one PCB to another, multiple PCBs connected together using embedded core laminates according to the present invention allows minimum cross-talk and characteristic impedance variations from one PCB to the next.

Abstract: A circuit board is provided having a plurality of vias and uniformly spaced connector stubs arranged upon one or both outer surfaces of the control board. Sets of trace conductors are formed within the control board between the vias. The trace conductors are arranged in two planes within the control board, wherein trace conductors within one plane are laterally offset from trace conductors in the other plane. Laterally offset trace conductors allow close spacing of the trace conductor planes while maximizing the spacing between trace conductors and corresponding reference conductors also placed within the control board. Additionally, the trace conductors are serpentine-shaped when viewed from a perspective perpendicular to the planar surface of the control board.

Abstract: A cooling subsystem and method for a chassis of a computer system. The cooling subsystem comprises: (1) first and second cooling fans having first and second motors associated therewith for driving the first and second cooling fans, respectively and (2) a common plenum substantially shrouding and providing a pathway for air communication between the first and second cooling fans, the first and second fans cooperating to provide an optimum rate of air flow from without the chassis to within the chassis to provide air exchange within the chassis, the air flow within the chassis being in a predetermined direction to provide directed cooling of a specified device within the chassis, the common plenum allowing the first and second fans to continue to cooperate to provide a minimum air flow to provide a minimum air exchange within the chassis, the air flow remaining in the predetermined direction to continue the directed cooling of the specified device when a selected one of the first and second motors fails.

Abstract: A detection system for detecting the insertion or removal of expansion cards having a standard edge connector using one or more capacitive plates coupled to corresponding variable frequency oscillators. The capacitive plates are preferably mounted on an internal layer of the expansion card and preferably aligned with corresponding pins of the edge connector for establishing capacitive loading with respect to the corresponding pins. The frequency of the oscillators change with changes in the capacitive loading of the corresponding plates. The detection circuitry includes a processor which continuously monitors the frequency of the oscillators to thereby detect movement of the expansion card, and preferably includes a control and isolation circuit which electrically isolates the power and data pins during insertion and/or removal as controlled by the processor. The detection circuitry may be mounted to either on the expansion card or the planar of the computer system.