Abstract: A voltage-controlled oscillator includes a voltage regulator, and a delay unit. The voltage regulator independently receives a first oscillation control signal and a second oscillation control signal to provide a regulated voltage signal which is represented by a regular ratio of combination of the first and second oscillation control signals, and the regulated voltage signal is feedback to the voltage regulator. The delay unit generates an output signal having a frequency varying in response to the regulated voltage signal.

Abstract: In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes a semiconductor substrate having buried contact landing pads and direct contact landing pads. A lower interlayer insulating layer is disposed on the semiconductor substrate. A plurality of parallel bit line patterns are disposed on the lower interlayer insulating layer to fill the direct contact holes. A passivation layer that conformally covers the lower interlayer insulating layer and the bit line patterns is formed. An upper interlayer insulating layer for covering the semiconductor substrate having the passivation layer is formed. Buried contact plugs are disposed in the upper interlayer insulating layer between the bit line patterns and extended to contact the respective buried contact landing pads through the passivation layer and the lower interlayer insulating layer.

Abstract: A video decoder removes noise caused by a luminance signal component when separating a chrominance signal from a composite video baseband signal. The video decoder includes a first signal generator generating a first signal, a second signal generator generating a second signal, a third signal generator differentiating the first and second signals and performing a predetermined operation on the differentiated signals to generate a third signal, an operating unit performing a predetermined operation on the third signal to output the chrominance signal, a fourth signal generator performing a predetermined operation on the first and second signals to generate a fourth signal having a value corresponding to the amplitude of the chrominance signal, and a noise removal unit correcting the chrominance signal in response to the third and fourth signals to remove luminance component noise included in the chrominance signal.

Abstract: A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

Abstract: A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

Abstract: A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a predetermined voltage, and the bit line sense amplifier including first and second transistors serially connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein a gate of the first transistor is connected to the complementary bit line and a gate of the second transistor is connected to the bit line.

Abstract: A wafer bonding method includes providing a primary wafer and a plurality of secondary wafers, wherein the primary wafer is larger than the secondary wafers. An intermediate material layer is formed on at least one of a bonding surface of the primary wafer and bonding surfaces of the secondary wafers. The intermediate material layer has a thermal expansion coefficient greater than the thermal expansion coefficient of the primary wafer and the thermal expansion coefficient of the secondary wafers. The secondary wafers are bonded onto the primary wafer.

Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

Abstract: A method of fabricating an image sensor includes forming a photoelectric transformation device on a substrate and forming a dielectric layer structure on the substrate. The dielectric layer structure includes multi-layer interlayer dielectric layers and multi-layer metal interconnections which are located between the multi-layer interlayer dielectric layers. A cavity which penetrates the multi-layer interlayer dielectric layers on the photoelectric transformation device is formed. A heat treatment is performed on the substrate on which the cavity is formed.

Abstract: Methods of fabricating light emitting elements and light emitting devices, light emitting elements and light emitting devices are provided. In some embodiments, the methods of fabricating a light emitting element includes forming a buffer layer on at least one first substrate, bonding the at least one first substrate on a second substrate, wherein the buffer layer is placed between each of the first substrate and the second substrate and the second substrate is larger than the first substrate, exposing the buffer layer, and sequentially forming a first conductive layer, a light emitting layer, and a second conductive layer on the exposed buffer layer.

Abstract: An inspection apparatus for containers, comprising a first illumination device which directs light having first characteristic properties onto the base of the container, a second illumination device which directs light having second characteristic properties, which differ at least partially from the first characteristic properties, onto the base of the container, and at least one image recording device which receives at least a portion of the light directed onto the base of the container and transmitted by the latter. At least the second illumination device illuminates the base of the container in an indirect manner.

Abstract: A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.

Abstract: In a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors, the stacked load-less SRAM device includes first and second transistors arranged in first and second active regions separately on a semiconductor substrate and third and fourth transistors arranged on first and second semiconductor layers over the first and second transistors. A first drain region of the first transistor, a third drain region of the third transistor, and a second gate of the second transistor are electrically connected through a first contact node. A second drain region of the second transistor, a fourth drain region of the fourth transistor, and a first gate of the first transistor are electrically connected through a second contact node.

Abstract: A method and an apparatus for indirectly simulating a semiconductor integrated circuit (IC) are described. A circle chain is formed using input pins and output pins to provide an intellectual property (IP) core model that substitutes for a real IP core circuit. A test bench for the IP core model is generated, the semiconductor IC that includes the IP core model is integrated using the generated test bench, and the semiconductor IC is simulated.

Abstract: A method for driving an image sensor includes the steps of: sensing temperature from the image sensor; selecting a voltage level of a control signal in accordance with the sensed temperature; and detecting an image in response to the control signal having the selected voltage level. An image sensor comprises a temperature sensor configured to sense a temperature of the image sensor and a pixel array configured to detect an image in response to a control signal, wherein the control signal varies in voltage level as a function of the sensed temperature.

Abstract: A photomask includes an ion trapping layer and a method of manufacturing a semiconductor device uses the photomask. The photomask includes a transparent substrate and an ion trapping layer formed on a first region of the transparent substrate to trap ions present near the transparent substrate. In manufacturing a semiconductor device, a photosensitive film formed on a substrate is exposed through the photomask in which the ion trapping layer is formed on the transparent substrate, and the substrate is processed using the photosensitive film obtained as the result of the exposure.

Abstract: In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

Abstract: A semiconductor integrated circuit having a switching variable resistance device with combined functions of a switching device and a variable resistance device is provided. The semiconductor integrated circuit includes a supply voltage input terminal that receives a supply voltage, a pulse generating unit that receives an input pulse and generates a variable amplitude pulse in response to the input pulse during a period of time, and a switching variable resistance unit that controls a current flowing into the supply voltage input terminal in response to the variable amplitude pulse, thereby limiting an inrush current and thus substantially reducing an temporary unstable effect on the supply voltage, which may be supplied from a power source.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.

Abstract: A multi-electrode system includes a fiber holder that holds at least one optical fiber, a plurality of electrodes arranged to generate a heated field to heat the at least one optical fiber, and a vibration mechanism that causes at least one of the electrodes from the plurality of electrodes to vibrate. The electrodes can be disposed in at least a partial vacuum. The system can be used for processing many types of fibers, such processing including, as examples, stripping, splicing, annealing, tapering, and so on. Corresponding fiber processing methods are also provided.