Abstract: A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.
Type:
Grant
Filed:
June 13, 2006
Date of Patent:
September 15, 2009
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Sung-dae Suk, Sung-young Lee, Dong-won Kim, Sung-min Kim