Abstract: A TAB semiconductor device (98) is manufactured with a TAB tape (62') which provides an intrinsic standoff for the device. The tape (62') has a carrier film (66'), having at least one cavity, and a plurality of conductors (64) on the top surface of the carrier film. A semiconductor die (42) is substantially centered either inside or below the cavity in the film. The conductors overlie bonding sites (44) on the active surface of the die. Inner-lead-bonds are made between the conductors and the bonding sites, wherein the conductors bend at the edges (65') of the cavity in order to contact the bonding sites, thus concurrently achieving a downset during the action of bonding. An encapsulant (99) provides protection to the die, the inner-lead-bonds, and a portion of the conductors.

Abstract: A self-opening vent hole semiconductor device (10) can be manufactured to reduce the risk of popcorning during solder reflow. The device contains a semiconductor die (22) mounted on a die mounting area (15) of a substrate (12). A venting hole (16) is approximately centrally located in the die mounting area. A venting hole sealing cap (20) covers and seals the venting hole. A layer of patterned solder resist (18) adheres to a lower surface of the substrate. The venting hole sealing cap can be made from the layer of solder resist, and can be configured to be either physically isolated from the solder resist layer or physically partially connected to the solder resist layer. The venting hole sealing cap is designed to be a weakest interface within the device so that it self-opens upon an internal pressure less than a destructive pressure to the device. Solder balls (30) provide external electrical connections for the device.

Abstract: A method and apparatus for providing a mask (200) on a multi-site wafer (100) is accomplished by first creating a first mask key (204) which contains information, such as alignment cues and test structures. A copy of the first mask key is modified to produce a second mask key (201). When the two mask keys are transferred to adjacent sites on the wafer, they physically overlap, preventing double-exposure of the information in the first mask key.

Abstract: This disclosure reveals a manufacturable and controllable method to fabricate a dielectric which increases the device current drive. A nitrogen-containing ambient is used to oxidize a surface of a substrate (10) to form a nitrogen-containing dielectric (12). Then a fluorine-containing specie (F) is introduced, preferably through implanting, into a gate electrode (20) overlying the nitrogen-containing dielectric. The fluorine is then driven into the underlying nitrogen-containing dielectric. A fluorinated nitrogen-containing region (14') is expected to form at the interface between dielectric (12') and substrate (10). The interaction between fluorine and nitrogen increases the peak transconductance as well as the transconductance at a high electric field for the dielectric. Therefore, the overall current drive is increased by this approach.

Abstract: A method for performing multiple field parallel processing in x-ray lithography uses a coupled mirror assembly (30) and a coupled mask assembly (22) to define and print multiple fields (54 & 54') in one step. The coupled mirror assembly (30) has multiple mirrored surfaces (34). The coupled mask assembly (22) has as many masks (44) as there are mirrored surfaces (34). The number of masks in the mask assembly define the number image fields that can be printed in parallel during a single exposure step. Thus, the overall cycle time for lithographically exposing an entire semiconductor wafer surface is inversely proportional to the number of parallel image fields.

Abstract: A preconditioning plate (10) prepares the surface of a polishing pad (24) to prepare the pad's surface for subsequent metal polishing of semiconductor wafers (27). The preconditioning plate has at least three intersecting radial ridges (14) on its surface and is made from a rigid plastic material. The preconditioning plate is rotated relative to the surface of the polishing pad prior to actual polishing to provide a uniform and stable polishing surface. The preconditioning plate does not abrade or wear away the polishing pad, nor does it form grooves in the polishing pad. Additionally, the preconditioning plate is reusable.

Abstract: A leadframe (30) having a novel resin injecting area (44) is disclosed to facilitate and control the removal of a molded gate (18) prior to excising a semiconductor device(70) from a carrier ring (14). The carrier ring has a corner which is on a diagonal with a corner of the package body (12) to form the resin injecting area. The resin injecting area of the leadframe has a hole (48) and an extension bar (50) extending from the hole to connect to a tie bar (36), which supports a die pad (32), inside the package body. The hole in the leadframe is designed for retaining a molded gate. The extension bar is designed to make the removal of a portion of a molded gate easier and more controllable. The semiconductor device can be shipped in the carrier ring with a portion of the molded gate already removed.

Abstract: A semiconductor die (14) is mounted over a power supply surface (24, 52, 62). Signal bonding pads (18) on the die are wire bonded to corresponding leads (38) of a leadframe. Power supply bonding pads (20, 21) on the die are wire bonded to the power supply surface. A package body (22, 42, 56) surrounds the semiconductor die, the wire bonds (32, 34, 40, 40'), and the power supply surface. The power supply pad terminals are accessible from the bottom of the package body of the device through a plurality of conductive apertures (28, 56) disposed in the lower half of the package body. Power supply solder bumps (12, 58) are connected to the power supply surface inside the package body through the conductive apertures. The leads are used provide input and out signals for the device around the periphery of the device, while the solder bumps are disposed in an array format on the package body.

Abstract: A tray (10') for handling a semiconductor device encapsulated in a package body and having multiple electrical I/Os projecting from the package body has cell-to-cell interlocking capability as well as invertibility. An interlocking nest feature (16) is formed on the underside of the tray and interfaces with the cells (12') on the topside of the tray (10') when the trays are stacked. The interlocking nest feature has an external chamfer (20) which mates with a lead-in chamfer (18) of the tray cell to align the interlocking feature (16) and the cell (12'). The interlocking nest feature (16) has an internal device retaining chamfer (22) and a device capture surface (26) to guide and retain the semiconductor device when stacking trays, inverting trays or processing semiconductor devices with the trays inverted. In-tray inspection and electrical test are also possible using a test contactor having a functional equivalent of the interlocking nest feature.

Abstract: A molded semiconductor device (24) having greater resistance to package cracking during board mounting in addition to increased thermal performance is provided wherein the device has a reduced semiconductor die to flag interface and a drop-in heat sink. The semiconductor die (12) is mounted on a leadframe (16) having a flag (15) with an opening to expose a substantial portion of the inactive surface (14) of the die (12). Decreasing the interfacial contact area between the die (12) and the flag (15) reduces the risk of package cracking during board mounting by limiting the area where delamination typically occurs. An encapsulant (22) forms a package body which encompasses an opening (23) to expose a substantial portion of the inactive surface (14) of the semiconductor die (12). A heat sink (26) is inserted into the opening (23), directly coupling the heat sink (26) to the die (12), after the semiconductor package is mounted onto a printed circuit board.

Abstract: Advances in wafer technology and packaging have led to an increase in wafer size while requiring a decrease in wafer thickness. Thickness limitations increase as wafer diameter increases. Thinning a wafer past a certain limit can result in wafer breakage. A laminated semiconductor wafer structure (10) is assembled to provide mechanical support for the wafer. A semiconductor wafer (12) is affixed to a UV transparent support substrate (16) with a double-sided adhesive tape (14). The tape has dissimilar adhesives on its two sides. The first side has a UV curable adhesive (22) that adheres to the active surface of the wafer. The second side has a non-UV curable adhesive (24) which adheres to the UV transparent support substrate. This laminated structure can be used during a wafer thinning process and any subsequent handling. The support substrate and the tape are removed from the wafer by exposing the laminated structure to UV radiation.

Abstract: A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder (60) with a vacuum (62) for the wire bonding process. Wire bonds (26) electrically connect the die to the conductors. The wire bonded die is then placed inside a mold cavity (64), and a resin encapsulated is transferred into the cavity under elevated temperature and pressure to form package body (70) around the die, the wire bonds and a portion of the conductors. Before the package body is formed, the die is supported solely by the the rigidity of the wire bonds since there is no die supporting surface connected to the conductors.

Abstract: An array type semiconductor device (10 and 40) has compliant polymer columnar I/O connections (30) to accommodate thermally induced stress during device operation. The device has a semiconductor die (22) mounted to a substrate (12) and electrically connected thereto. A package body (28, 46) covers the semiconductor die and electrical connections (26, 42) to provide mechanical protection. The I/O contacts are formed from a polymer core (34) that is metallized to impart electrical conductivity to the contacts. The metallization (36, 38) may either be a plating around the polymer core or fillers embedded in the polymer. The aspect ratio of the polymer contacts is greater than one to provide compliance while maintaining high I/O density in the array. The metallized polymer contacts may be attached to the package substrate and to a PWB with joints (32) composed of either solder or a conductive adhesive.

Abstract: A nodular metal paste (42) is used to temporarily attach the bumps (34) on a semiconductor die (32) to a substrate (38). The spherical nodules (44) composing the metal paste are dispensed onto contact pads (40) on the substrate, and then heated until they partially melt. The partial liquid region permits bonding of the individual metal nodules to the contact pads and to adjacent nodules. Subsequently, a bumped die is placed over the nodules and heated to a minimum temperature required to partially remelt to form a local tack joint. Because the metallurgical contact area between the paste nodules and the bumps is minimized, electrical contact can be sustained with a small cross-sectional area of connected material to create an electrically sound but physically weak link between die and the substrate. Once connected to the substrate, the die may be tested and burned-in, and removed afterwards with little damage to the bumps.

Abstract: A method for making a vertical profile contact opening (18) uses an etch stop layer (14), interposed between a conductor layer (10) and a dielectric layer (16), to eliminate resputtering of the underlying conductor material which prevents tapering of the etched opening (18). This contact opening formation is accomplished using different etchant chemistries, etching one film selective to the other. The use of the etch stop material in conjunction with conventional interconnect structures allows multiple stacking of contact features or multilevel interconnects to be achieved independent of underlying topography without increasing overall contact/via resistance. The method allows the fabrication of an unlanded via structure (30) having substantially vertical sidewall profile.

Abstract: A thermally enhanced semiconductor device (10) having an exposed backside (22) is described. In one embodiment, a PC board substrate (12) is provided having a pattern of conductive traces (14) on both upper and lower surfaces of the substrate. Electrical continuity is maintained between the two surfaces with conductive vias (16). A semiconductor die (18) is flip-mounted to the upper surface of the substrate. Solder bumps (26) electrically connect the die to the conductive traces, and an underfill (28) couples the active side (20) of the die to the upper surface of the substrate. A package body (40) is formed around the perimeter (24) of the die leaving the inactive backside exposed for enhanced thermal dissipation. The inactive backside can also be coupled to a heat sink for increased thermal dissipation. A plurality of solder balls (42) electrically connected to the conductive traces is attached to the lower surface of the substrate.

Abstract: A wedge bond tool tip (20, 30, 50, 56) for bonding electronic interconnects to bonding pads of a semiconductor device enables fine-pitch non-orthogonal wire bonding. The tool tip (20, 30, 50, 56) has an overall width and a front face (12', 52) that has a reduced area which is narrower than the overall width. The reduction in the front face is accomplished through either chamfering or rounding of the corners to reduce the contact distance (42 and 44) between the wedge tool and a previously made adjacent bond. This design maintains the structural integrity needed to produce acceptable wedge bonds.

Abstract: A compliant integrated circuit (IC) wiring substrate (10) has an insulative carrier film (14) and a plurality of micro-beam conductors (12) in the carrier film. Each of the plurality of micro-beam conductors has a pair of contact bumps (16 and 18) connected to respective posts (22 and 24). A beam element (20) connects the pair of contact bumps and posts at opposing ends and opposing surfaces of the beam element. The plurality of micro-beam conductors extend through the thickness of the carrier film such that the pair of contact bumps protrude from the opposite surfaces of the carrier film. The compliance of the wiring substrate can be varied by varying locations of apertures in the insulative carrier film.

Abstract: The accuracy of pre-treatment radiographic images is improved by standardizing a technique for placing a bite block in a patient's mouth, by minimizing distortion in the resulting radiograph, and by providing a means for measuring the remaining distortion in the radiographic image. The placement of the bite block is registered on study models prior to the taking of the radiograph such that the dental practitioner can predetermine the best possible position for the bite block per individual patient outside the patient's mouth. The best possible position allows the dental practitioner to optimize the position of the bite block to obtain a radiograph having minimal vertical distortion and mesio-distal distortion. As some distortion is inevitable, the invention also allows for a means to measure the resulting distortion based on spatial markers set at a predetermined distance apart which are superimposed onto the radiographic image.

Abstract: A mixed thin-film and bulk semiconductor substrate (10, 30) for integrated circuit applications is made with two different processes. In the first process, a standard wafer (11) is masked around its periphery (14). The internal unmasked portion (16) is implanted with an insulating species to form a buried dielectric layer (18), thus forming a mixed thin-film and bulk semiconductor substrate. Alternatively, a thin-film wafer may be masked on an internal portion (36) and then etched to expose a portion (40) of the underlying bulk substrate (11') around the periphery of the wafer. An epitaxial layer (50) is then grown to build up the exposed bulk portion to form the mixed substrate. An isolation region (24, 52, 46, 54) is formed at a boundary between the thin-film portion and the bulk portion. Devices (27, 28, 28') having different voltage requirements may then be formed overlying appropriate portions of the mixed substrate.