Abstract: A SIMOX structure having a reduced number of defects is formed by performing a two step anneal. In one embodiment, a conventional anneal is followed by an H.sub.2 /Si anneal. The conventional anneal first densifies the buried oxide layer in order to make the oxide less reactive with hydrogen. The H.sub.2 /Si anneal forms a quasi-equilibrium at the superficial semiconductor layer surface, thus there is no etching of the silicon surface and there is only a negligible amount of silicon deposition. The H.sub.2 reacts with the oxide precipitates and dissolves them. In a second embodiment the two step anneal comprises a low temperature H.sub.2 anneal followed by a conventional anneal. At low temperature, H.sub.2 can diffuse through silicon, but is much less reactive. Thus, etching of the superficial silicon and silicon dioxide buried layer is minimal. The conventional anneal is at a higher temperature, thus H.sub.2 can react with the oxygen precipitates to remove them.

Abstract: Bond tool pressure distribution is optimized by a method and apparatus having a device having a first surface which permits inclination of the first surface in at least one direction, wherein the device is in a locked position. A first bonding arrangement is positioned on the first surface of the device. A second surface makes contact to the first bonding arrangement. This contact is detected and the device is unlocked to allow the first surface to incline while the second surface is in contact with the first bonding arrangement. The second surface is applied to the first bonding arrangement with a force, and the device is locked upon application of the force.

Abstract: Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.

Abstract: A semiconductor device having a channel region having a first and a second portion. The first and second portions of the channel region are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

Abstract: A non-silicon substrate is bonded to a silicon substrate with a stress-relief layer between the non-silicon substrate and the silicon substrate. The stress-relief layer reduces the stress between the non-silicon substrate and the silicon substrate. The stress is created by the difference in the thermal expansion coefficients of the two materials. The stress-relief layer may be a low melting point metal, a semiconductor layer having its thermal expansion coefficient close to the thermal expansion coefficient of the non-silicon substrate. The silicon substrate and/or the non-silicon substrate may have a silicon dioxide layer formed thereon such that the silicon dioxide layer is adjacent to the stress-relief layer.

Abstract: A fast and simple method of determining a desired level of cleanliness of an inorganic surface is performed by correlating a level of cleanliness of many inorganic surfaces having varying thicknesses of organic contamination with reliability tests. The level of cleanliness is in terms of a measurement from a water drop test. The level of cleanliness between two inorganic surfaces can also be compared by utilizing the combination of a UV/ozone clean and the level of cleanliness to determine the relative amount of contamination present on one inorganic surface as compared to the other.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Abstract: A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.

Abstract: A multi-tiered contact etch process comprising alternating anisotropic and isotropic etch steps is performed in a reactive ion etcher wherein DC bias on a cathode (11) of the etcher can be controlled independently from RF power, adding a great deal of control over isotropy of the etching. By shunting the cathode (11) directly to ground a high level of isotropy is achieved during isotropic etch steps. When the cathode (11) is not shunted to ground a bias voltage develops on the cathode (11) providing a highly anisotropic etching.

Abstract: A method of producing reliable bonds of a lead to a bump on a semiconductor chip is accomplished by controlling the amount of deformation of the lead and the bump during bonding. A differential amplifier is used to sense the deformation and stop the application of force to the lead and the bump when a desired amount of deformation of the lead and the bump is obtained.

Abstract: The reverse breakdown voltage of a conventional insulated gate transistor is greatly increased by the addition of a lightly doped layer between the substrate and a buffer layer of the insulated gate transistor. The addition of the lightly doped layer does not increase the on resistance of the device, nor the cut-off time of the device. The lightly doped layer can be provided as an epitaxial layer along with the other epitaxial layers of the insulated gate transistor.

Abstract: An improved TAB bond is achieved by an apparatus for tape automated bonding, comprising a thermode having a bonding surface. A shield is attached around the bonding surface. The shield is designed so that a nonoxidizing gas may be distributed in a bonding space defined by a plurality of tape leads on a tape positioned below the shield and a bonding area of a semiconductor chip positioned below the tape and the plurality of tape leads. In the bonding position the flow of the nonoxidizing gas removes substantially all of an ambient air in the bonding space.

Abstract: A substantially planar semiconductor surface is formed for fabricating submicron BiCMOS integrated circuits. A lightly doped epitaxial layer is formed on a semiconductor substrate having buried layers formed therein. The substantially planar semiconductor surface is formed by forming a p-type well in the lightly doped epitaxial layer before the step of forming an n-type well in the lightly doped epitaxial layer.

Abstract: A vertical cavity surface emitting laser (VCSEL), comprised of a first 1/4 wave stack, an active layer and a second 1/4 wave stack, is integrated with a heterojunction bipolar transistor (HBT). The HBT is partially or fully positioned within either the first or the second 1/4 wave stack of the VCSEL. This method improves the planarity of the device, thus allowing for high performance devices to be fabricated. A top or bottom emitting device may be fabricated with the second 1/4 wave stack comprised of dielectric layers or semiconductor epitaxial layers.

Abstract: A reduction in defects and lateral encroachment is obtained by utilizing a high pressure oxidation in conjunction with an oxidizable layer conformally deposited over an oxidation mask. The use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited.

Abstract: A semiconductor structure having an improved polysilicon layer is formed. After the formation of a silicon dioxide layer over a semiconductor wafer, the semiconductor wafer is heated in an ambient comprised of nitrogen. The heating is preferably accomplished so that nitridation of the silicon dioxide does not take place. Subsequently, a polysilicon layer is formed on the silicon dioxide layer. The polysilicon layer is denser and thus more resistant to hydrogen fluoride than polysilicon formed without exposing the silicon dioxide layer to nitrogen.

Abstract: An improved process is described for depositing TiW/TiWN/TiW/Au metallization which provides superior adhesion properties, excellent barrier properties and which is suitable for use with metal line widths of the order of one micron or smaller. It is important in order to obtain these properties to ensure that the layer immediately underlying the gold layer by substantially pure TiW deposited in a nitrogen free sputtering atmosphere. To this end, the gas supply manifolds and deposition chamber are purged and the chamber evacuated following deposition of the TiW layer and prior to deposition of the TiWN layer underlying the gold layer. A final TiW layer is also conveniently placed on top of the gold layer to act as an etching mask.

Abstract: A planar semiconductor laser having low thermal and series resistance is fabricated. The semiconductor laser has an optical waveguide and a lateral current injection path provided by a conductive region. The conductive region disorders the active region and the first 1/4 wave stack of the laser, which reduces the reflectivity, therefore allowing control of the optical waveguide independent of the current flow. By forming the conductive region, the laser of the present invention can have stable optical characteristics and a bigger emission spot due to the weak built-in waveguide, thus resulting in the formation of a device having high output and a low thermal and series resistance.

Abstract: A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.