Abstract: A method of video decoding is provided that includes receiving a data stream comprising a sequence of syntax elements that were compressed using context-adaptive binary arithmetic coding (CABAC), such that the encoding of each bin of a bin string representative of a syntax element was performed by arithmetic encoding. Two consecutive bins of a syntax element are decoded in parallel. Speculative computation and prefetching is used to reduce the critical path and thereby improve processing speed.

Abstract: Bandwidth expansion for audio signals by frequency band translations plus adaptive gains to create higher frequencies; use of a common channel for both stereo channels limits computational complexity. Adaptive cut-off frequency determination by power spectrum curve analysis, and bass expansion by both fundamental frequency illusion and equalization.

Abstract: Audio loudspeaker and headphone virtualizers and methods use room impulse responses with modified individual head-related transfer functions prior to superposition including middle truncation; and perform convolutions in the frequency domain with zero-padded sections to avoid circular convolution overlap.

Abstract: High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

Abstract: An interface unit is provided for selectively testing a plurality of processor/cores. The interface unit includes an interface test access port (TAP) unit operable to receive test commands, and a logic unit coupled to the interface TAP unit and operable to generate control signals based on the received test commands to selectively generate a configuration of TAP units comprised in the plurality of processor/cores to receive test signals.

Abstract: Digital camera color correction with a linear transformation having coefficients computed from an optimization with preservation of gray levels. This preserves white balance despite differing exposures for images from a target sensor and reference colors.

Abstract: Bandwidth expansion for audio signals by frequency band translations plus adaptive gains to create higher frequencies; use of a common channel for both stereo channels limits computational complexity. Adaptive cut-off frequency determination by power spectrum curve analysis, and bass expansion by both fundamental frequency illusion and equalization.

Abstract: Graphic equalizer as a cascade of equalization filters with the gain of each individual filter compensated for the gain leakage from other filters. A linear approximation allows individual filter gains to be set to give desired frequency responses.

Abstract: A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.

Abstract: Inverse discrete cosine transform (type-III DCT), used in video/image and audio coding, is implemented in the form of FFT to lower computational complexity.

Abstract: A method for merging branch information with sync points is disclosed herein. The method comprises determining whether a sync point is to be generated concurrent with a branch instruction and generating said sync point to include a program counter value and to indicate that the sync point occurred concurrent with the branch instruction.

Abstract: Layered code-excited linear prediction (CELP) speech encoders have progressively weaker perceptual weighting filters for each of the successive enhancement layers and decoders have progressively weaker short-term postfilters for increased bit rates (increased number of enhancement layers decoded) and a long-term postfilter for all bit rates.

Abstract: A system comprising a processor core adapted to execute software code and a trace logic coupled to the processor core and comprising a storage. The storage comprises at least one bit that indicates a condition and status information. The trace logic generates a trace information stream associated with the processor core as the core executes the software code. If the condition is satisfied, the trace logic adjusts a status of the trace stream in accordance with the status information.

Abstract: Layered (embedded) code-excited linear prediction (CELP) speech encoders/decoders with adaptive plus algebraic codebooks applied in each layer with fixed codebook pulses of one layer used in higher layers. Pulse weightings emphasize lower layer pulses relative to the higher layer pulses.

Abstract: The present invention relates to a CMOS buffer circuit for liquid crystal display (LCD) drivers, which includes a single stage operational transconductance amplifier (OTA) with a differential of transistors for receiving a differential input voltage, a bias current source coupled to the differential pair and a single-ended output, the first bias current generating stage with a differential pair of transistors coupled to receive the differential input voltage to produce an output current in an output current path in response to a positive differential input voltage, a second bias current generating stage with a differential pair of transistors coupled to receive the inverted differential input voltage to produce an output current in an output current path in response to a negative input voltage, wherein the output current paths of both bias current generating stages are combined in a common current path and the current in the common current path is mirrored to the bias current source of the single stage OTA, s

Abstract: Speech or musical performance is electronically analyzed using DSP techniques and is compared to a stored text script or musical score, to enable display of and automated sequencing through multiple pages of the stored script or score. The performer can modify timing of sequencing if desired, for example dependent on performance speed or musical complexity. Automated highlighting or marking of measures or text assists the performer in keeping track of progress through the performance. During or after the performance, electronic comparison of the performance to the score or script provides feedback to the performer, highlighting differences between the actual performance and the desired performance as described by the score or script.

Abstract: Hands-free phones with voice activity detection using a comparison of frame power estimate with an adaptive frame noise power estimate, automatic gain control with fast adaptation and minimal speech distortion, echo cancellation updated in the frequency domain with stepsize optimization and smoothed spectral whitening, and echo suppression with adaptive talking-state transitions.

Abstract: Packetized CELP-encoded speech playout with frame truncation during silence and frame expansion method dependent upon voicing classification with voiced frame expansion maintaining phasealignment.

Abstract: A method and apparatus for scheduling in a wafer fab. The method comprising means for weighting inventories according to at least one of logpoints or reticle, and photolithography units, means for scheduling one of said inventories on one of said photolithography units, wherein said one of said inventories has a maximal weighting and means for eliminating any of said inventories not scheduled according to constraints.

Abstract: An integrated programmable device has a plurality of signal inputs (P1, P2, P3) connected to respective ones of a plurality of switching elements (S1, S2, S3). Each switching element (S1, S2, S3) has an associated enable line (E1, E2, E3). A control circuit (15) activates one or more selected signal inputs (P1-P3) in accordance with a channel select signal (16) via these enable lines (E1, E2, E3). Feedback lines (F1, F2, F3) are connected to corresponding enable lines (E1, E2, E3) to a channel feedback indicative of which signal inputs (P1, P2, P3) is enabled. This allows determination whether the enabled signal inputs (P1, P2, P3) correspond to the channel select signal (16) and initiates an exception handling in case of a mismatch. The comparison can be performed by a compare logic circuit (40) or the channel feedback can be stored in a memory (30) accessible by a software program (60), which performs the comparison.