Abstract: A circuit to conveniently and safely drive an electronic calculator from a source of ac power or, alternately, from either one of a plurality of disposable batteries or a unique, rechargeable battery pack. The present circuit includes an arrangement of contact means particularly positioned in a predetermined relationship within the battery compartment of the calculator and on the rechargeable battery pack. When disposable batteries are deposited inside the battery compartment of the calculator and an ac adapter accessory is connected to provide power to the calculator, the disposable batteries are electrically isolated from the ac source. However, when the rechargeable battery pack is deposited inside the battery compartment of the calculator and the ac adapter is connected to provide power to the calculator, the battery pack is recharged.

Abstract: An effective, low cost block and brace assembly having utility in the art of tilt-up construction. In the assembled relationship, the block and brace form a right triangle to provide maximum support for a mold form during the pouring of concrete and the subsequent formation of a precast panel.

Abstract: An improved assembly is disclosed to orient and immobilize the head of a patient for the purpose of taking x-ray pictures. The size of the assembly is adjustable to readily fit different patient accomodating means (e.g. a table, chair or the like). The assembly is free to move in any of a plurality of directions in order to conveniently engage the head of the patient. The assembly can be moved out of the way of the patient so as to allow easy access to or exit from the patient accomodating means.

Abstract: A compact circuit for selectively controlling the operation of a plurality of metal oxide semiconductor field effect transistors (MOSFETs) which drive a readout display, such as that found in a hand-held calculator, or the like. The circuit includes an internal power supply to develop a driving voltage (V.sub.gg), the magnitude of which is substantially boosted with respect to that of the calculator operating voltage (V.sub.DD). The circuit also includes an improved strobe driver connected between the display and the power supply to selectively apply the boosted driving voltage to a control electrode of any one of the plurality of MOSFETs.

Abstract: An improved dynamic logic gate compatible with a four-phase, major-minor clocking scheme and a six-phase metal oxide semiconductor (MOS) system. The gate evaluates only during an in-between clock phase, which phase corresponds to the interval of time between the occurrence of first and second major clock phases.

Abstract: A buffered serial to parallel memory system uses an output driver which is semi-independently operated by separate control logic. Following conventional serial data input to a first buffer, the separate control logic responds to a predetermined signal to independently clear a second buffer, transfer the data from the first buffer to the second buffer and then clear the first buffer for further data input. The stored data in the second buffer is then used for output devices requiring parallel data output.

Abstract: An improved, compact high-speed inverting power driver fabricated from field effect transistors and capable of driving a relatively heavy load to full -V.sub.DD power supply voltage. The power driver includes a pair of positive feedback circuits having respective bootstrap capacitors arranged therein. The bootstrap capacitors are initially precharged, and the feedback paths act to substantially boost the voltage applied to operate a driver transistor so as to enable the load to be ultimately driven to a full -V.sub.DD voltage level via the conduction path of the driver transistor.

Abstract: An improved MOS clamping circuit compatible with a multi-phase, major-minor clocking scheme. The present circuit is adapted to clamp the output terminal of a conventional major logic gate to a negative signal level. The instant clamping circuit prevents the deterioration of the logic gate output signal as a consequence of positive noise during the minor clock phases and during an in-between clock phase, which phase corresponds to the interval of time between the occurrence of first and second major clock phases.

Abstract: An electronically programmable frequency correction arrangement. The frequency of a source input signal is compared to a desired frequency. Pulse stuffing techniques are utilized by which a number of pulses comprising a frequency correction signal are selectively added to the input signal so as to accurately adjust the source frequency to the desired frequency.

Abstract: A unique sense circuit to implement a differential memory detector having increased sensitivity for reading the binary state of selected memory cells forming an array thereof. The detector, in a preferred embodiment, includes a circuit comprised of a plurality of metal oxide semiconductor field effect transistors fabricated from a layer of silicon on sapphire (SOS/FETs). The body node of each of a pair of SOS/FETs is respectfully connected to a data bus line of the memory array so as to form differential input nodes to the detector circuit. The instant detector circuit provides relatively large digital output signals from relatively small input signals supplied from the array of memory cells via the data bus lines.

Abstract: A time delay circuit comprising an improved charge transfer scheme for use in a microelectronic circuit, such as, but not limited to, a calculator, and the like. The circuit efficiently charges a capacitance means with a signal to subsequently energize a utilization means. Sufficient time delay is provided when charging the capacitance means, after power is applied to the microelectronic chip means and before the utilization means is suitably energized, to insure that associated logic is first initialized and sources of reference potential are at proper operating levels.

Abstract: A unique one chip counter arrangement and high-speed test circuit for an electronic timing device, such as a digital watch or clock. The counter arrangement is comprised of a plurality of separate divider stages interconnected with respect to one another in order to be rapidly tested in either a test mode or to be operated in a normal mode of operation by a minimum number of components which consume a relatively small amount of space.

Abstract: Circuitry having a unique strobing scheme to effectively drive both a light-emitting diode display and an associated keyboard directly from a single semiconductor chip. The circuitry accurately senses which of the keyboard keys is in a depressed condition in order that a suitable representation thereof may be displayed at an appropriate time.

Abstract: An improved very high speed, static random access memory cell disclosed which is comprised of complementary metal oxide semiconductor field effect transistors which may be formed by silicon on sapphire techniques. To maximize the speed of the read operation while, at the same time, decreasing the overall cell area and consequently the cost, the cell is made highly non-symmetrical in design. As an example, selected ones of the semiconductor transistors may have reduced channel widths with respect to one another.

Abstract: Unique, relatively simplified circuits employing complementary metal oxide semiconductor transistors and suitable diode means to mechanize the Boolean functions A.sup.. B and A+B and combinations thereof. In a preferred embodiment, the transistors and diodes may be fabricated by silicon-on-sapphire integrated circuit techniques. The circuits obviate the need for a conventional NOR or NAND gate which is common to logic gating arrangements of the prior art. Hence, the number of components and the corresponding cost of the circuit are reduced while the operating speed thereof is increased.

Abstract: A uniquely arranged, clock-controlled integrated circuit is disclosed as a building block for implementing Boolean logic functions. The circuit has a minimum number of components and a design to yield a low cost, high speed operation. The circuit may also include an efficient signal inversion and amplification stage, where such is required.

Abstract: A unique, two-node sense circuit is disclosed. The circuit includes a bridge comprised of resistance elements and a differential amplifier. The two-node circuit is suitably adapted to be arranged in an array comprised of a plurality of discrete bridge-amplifiers which can be selectively energized. The circuit is arranged so as to form a configuration with minimum power utilization and a reduced number of components and interconnections therebetween.

Abstract: An integrated circuit is disclosed providing the logic to generate a unique binary coded numerical counting sequence and a corresponding decoded segment select sequence to subsequently activate particular segments comprising a display pattern at predetermined times. A minimum number of logic input terms and respective logic gates are required to implement the instant sequence to thereby reduce the space consumed by the circuit and the cost thereof.

Abstract: A process for making an interconnect system for a multilayer circuit pattern. The interconnect system is formed having minimized through-hole space consumption so as to be suitable for high density, closely meshed circuit patterns.

Abstract: A driver circuit which has low power requirements, a relatively small number of components and provides flexibility in output voltage setting. The driver circuit comprises, essentially, two portions which are selectively activated by the application of input signals. The output signal is determined by which of the two circuit portions is activated. While each of the two circuit portions operates in a manner similar to silicon controlled rectifiers (SCR), the circuit portions are on only when an input signal is supplied thereto.