Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes.

Abstract: An assembly for conducting an electronic signal. The assembly includes a substrate and an electronic cable. The substrate has distinct first and second regions to enable connection to first and second circuit boards, respectively. First and second through-holes are formed in the substrate in the first and second regions, respectively. The electronic cable is disposed within the first through-hole and extends out of the first through hole, adjacent the substrate and into the second through-hole.

Abstract: An object of the present invention is to provide a single-phase film of a metal sulfide with good quality, and a method for preparing a metal sulfide film at a low cost in a convenient manner. The present invention provides a preparation method of a metal sulfide film, comprising the steps of providing metal halide, such as iron halide (FeCl3, FeI3, FeBr3, FeCl2, FeI2 and FeBr2), as a first raw material and a thioamide compound, such as thioacetamide, as a second raw material, preferably vaporizing these raw materials and reacting them at atmospheric pressure; and a metal sulfide film prepared by this method.

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

Abstract: A light emitting device package assembly includes a light emitting device package body, and first, second and third white light emitting devices on the package body, each of the first, second and third white light emitting devices emits light when energized having a chromaticity that falls within a respective one of first, second and third non-overlapping chromaticity regions in a two dimensional chromaticity space. The first, second and third chromaticity regions are spaced apart in the two dimensional chromaticity space by respective regions having at least the size of a seven step MacAdam ellipse. Related solid state luminaires and methods are also disclosed.

Abstract: Methods of operating a transceiver including an antenna having a plurality of antenna feed elements include providing a plurality of gain constraint values associated with respective ones of the plurality of geographic constraint points within a geographic region, selecting initial phase constraint values associated with respective ones of the gain constraint values, generating antenna feed element weights based on the gain constraint values and based on the initial phase constraint values, and determining system response values in response to the antenna feed element weights. Phases of the system response values are compared to the initial phase constraint values, and an antenna beam is formed from the antenna to the geographic region using the antenna feed element weights in response to the comparison of the phases of the system response values to the initial phase constraint values. Related systems and devices are also disclosed.

Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

Abstract: A semiconductor device including vertical field effect transistors may comprise a buried insulating film stacked on a semiconductor substrate and spaced apart first and second active regions vertically penetrating the buried insulating film. The active regions and the buried insulating film are covered with an interlayer insulating film. An upper interconnection is disposed in the interlayer insulating film. A gate electrode extends from a part of the upper interconnection into the buried insulating film between the first and second active regions. A protective film pattern is disposed to cover a top surface of the upper interconnection. First and second buried contact electrodes penetrating the interlayer insulating film to be in contact with top surfaces of the first and second active regions are provided. Related manufacturing methods are also described.

Abstract: A method for positioning a guide device for placement of an interventional object in a body, the guide device having a guide axis, includes: determining a target point in the body and a reference point, wherein the target point and the reference point define a planned trajectory line (PTL) extending through each; determining a visualization plane, wherein the PTL intersects the visualization plane at a sighting point; mounting the guide device relative to the body to move with respect to the PTL, wherein the guide device does not intersect the visualization plane; determining a point of intersection (GPP) between the guide axis and the visualization plane; and aligning the GPP with the sighting point in the visualization plane.

Abstract: A method for determining a position of a mobile device may include receiving a communication signal at the mobile device simulcast from a plurality of transmitters. One of the plurality of transmitters is identified based on information obtained from the received simulcast communication signal, and an identifiable signal associated with the identified one of the plurality of transmitters is received at the mobile device. A range of the identified one of the plurality of transmitters from the mobile device is determined based on the received identifiable signal.

Abstract: Display devices include a display driving circuit, which is configured to generate a source driving signal and a gate driving signal in response to image data and horizontal and vertical sync signals. This display driving circuit includes a resolution-type generator, a timing controller, a source driving circuit and a gate driving circuit. The resolution-type generator is configured to generate a resolution-type signal in response to a resolution selecting code and the timing controller is configured to generate first image data, a source driver control signal and a gate driver control signal in response to the resolution-type signal, the image data and the horizontal and vertical sync signals. The source driving circuit is configured to generate the source driving signal in response to grayscale voltages, the first image data and the source driver control signal. The gate driving circuit is configured to generate the gate driving signal in response to the gate driver control signal.

Abstract: Integrated circuit memory devices include a semiconductor word line having an electrically insulating strain layer directly contacting an upper surface thereof. The strain layer, which has a contact opening therein, has a sufficiently high degree of internal compressive strain therein to thereby impart a net tensile stress within at least a first portion of the semiconductor word line. A P-N junction diode is also provided on the semiconductor word line. The diode includes a first terminal (e.g., cathode, anode) electrically coupled through the opening in the strain layer to the surface of the semiconductor word line. A data storage element (e.g., MRAM, FRAM, PRAM, RRAM, etc.) may also be provided, which has a current carrying terminal electrically coupled to a second terminal of the p-n junction diode.

Abstract: An oscillator for use in generating a signal having a desired frequency includes a first inductor element being electrically coupled from one end of a first capacitive element to a first voltage connection point, a second inductor element being electrically coupled from one end of a second capacitive element to a second voltage connection point, a third inductor element being electrically coupled from another end of the first capacitive element to the first voltage connection point, a fourth inductor element being electrically coupled from another end of the second capacitive element to the second voltage connection point. The first, second, third, and fourth inductor elements being configured such that a first conductive trace loop formed by the first and third inductor elements is interleaved with a second conductive trace loop formed by the second and fourth inductor elements such that said conductive trace loops are configured to operate in substantially a same magnetic field.

Abstract: A submersible object management (SOM) system for releasing and/or recovering a plurality of submersible objects within a body of liquid includes a hold and a deployment system. The hold is configured to store the plurality of submersible objects. The deployment system is selectively operable to controllably release at least one of the plurality of submersible objects from the hold into submersion in the body of liquid and/or selectively operable to controllably direct at least one of the plurality of submersible objects into the hold from submersion in the body of liquid. The deployment system includes a guide that is selectively extendable to direct the at least one submersible object, the guide including a plurality of extendable guide members configured to engage the at least one submersible object.

Abstract: Provided is a semiconductor memory device supporting a read data bus inversion (RDBI) function and a method of testing the semiconductor memory device. The method includes: providing data of an input test pattern to data input/output pads; including the data of the input test pattern in a data bus through a memory cell core block; if the data on the data bus satisfy an inversion condition, inverting and outputting the data on the data bus, and generating a flag signal indicating that the data on the data bus are inverted; comparing each of the inverted data on the data bus with the flag signal and transmitting resultant data to the data input/output pads; and determining whether the resultant data transmitted to the data input/output pads are data of an output test pattern.

Abstract: Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction toward a side of the bit-line stack and a connection line that extends in a horizontal direction to connect the plurality of local word-lines with one another, and forming a resistance memory thin film between the bit-line stack and the word-line. The present inventive concept can realize a highly dense memory array with 3D cross-point architecture by simplified processes.

Abstract: Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).

Abstract: Devices are provided for facilitating connection of at least one element to a pole of a battery. The devices include an adapter including a first portion of the adapter and a second portion of the adapter. The first portion of the adapter is configured to attach to the pole of the battery and the second portion of the adapter includes at least one protruding member. The at least one protruding member is configured to receive the at least one element and is electrically connected to the first portion of the adapter. The device further includes a protective lid configured to be received by the adapter and to provide an electrically insulating cover for the at least one protruding member.

Abstract: A polarization grating includes a substrate and a first polarization grating layer on the substrate. The first polarization grating layer includes a molecular structure that is twisted according to a first twist sense over a first thickness defined between opposing faces of the first polarization grating layer. Some embodiments may include a second polarization grating layer on the first polarization grating layer. The second polarization grating layer includes a molecular structure that is twisted according to a second twist sense that is opposite the first twist sense over a second thickness defined between opposing faces of the second polarization grating layer. Also, a switchable polarization grating includes a liquid crystal layer between first and second substrates.