Patents Represented by Attorney, Agent or Law Firm Myers, Bigel, Sibly & Sajovec
  • Patent number: 8207033
    Abstract: Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-Sun Kim, Hwa-Sung Rhee, Ho Lee, Ji-Hye Yi
  • Patent number: 7734698
    Abstract: Embodiments of the present invention include methods, terminals and circuits for updating provisioning data of a mobile terminal. A network initiated subsequent provisioning message requesting that the mobile terminal initiate a session to update the provisioning data of the mobile terminal is received and it is determined if the mobile terminal is executing a foreground data application utilizing a current registered Internet Protocol (IP) session. An IP session is selectively initiated to update the provisioning data of the mobile terminal based on the determination of whether the mobile terminal is executing a foreground data application utilizing a current registered IP session.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: June 8, 2010
    Assignee: Sony Ericsson Mobile Communications AB
    Inventors: Samuel L. Mullis, II, Scott G. Hicks
  • Patent number: 6762122
    Abstract: Metallurgy structures for input/output pads of an electronic devices can be adapted to receive both solder and wire bonds. First and second metallurgy structures, for example, can be provided on respective first and second input/output pads of an electronic device such that the first and second common metallurgy structures have a shared structure adapted to receive both solder and wire bonds. A solder bond can thus be applied to the first metallurgy structure, and a wire bond can be applied to the second metallurgy structure.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 13, 2004
    Assignee: Unitivie International Limited
    Inventors: J. Daniel Mis, Kevin Engel