Abstract: A split bus architecture which separates the processor/processors and the procedure memory coupled to a microprocessor (.mu.P) bus from all direct memory access (DMA) devices coupled to a DMA bus. A coupler mechanism provides bus isolation of the microprocessor bus from the DMA bus and permits the processor to access devices on the DMA side when addressed. This separation allows data transfers to proceed on one side of the bus without interfereing with software execution on the other side of the bus.

Abstract: An apparatus and a method for interfacing a commercially-available programmable communication interface (PIC) with a magnetic swipe reader or a wand type reader. The invention modifies the raw signals of the magnetic wand and magnetic swipe readers by removing noise and selecting the appropriate reader and track, stretching the clock pulses of the reader, and latching data into a flip-flop until the data is strobed into the PIC.

Abstract: A method for printing composite characters in a word processing system by multistriking two or more characters in the same character space. This method allows composite character graphics to be produced by using individual character graphics found within the character set of the output device. The method provides for the vertical and/or horizontal offsetting of the printhead between the striking of individual characters which form the composite character.

Abstract: Local area network control block (LCB) hardware and a method is disclosed which forms a prime vehicle of intercommunication between controller coupled local area networks (LANs), comprising a plurality of computer systems. An LCB has a predetermined format and is assembled by the computer hardware to provide information to the controller regarding the routing and transfer of a variable quantity of data between LANs.

Abstract: In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work of an entire semaphore operation such that the simple part of the P and V operations (which deliver and pick-up signals to and from the processes, respectively) is done by the firmware; whereas the difficult work of the P or V operation is done by software. Thus the improved architecture increases the speed of the system by the use of firmware and increases the flexibility of the computer system by utilizing software to change functionality.

Abstract: The invention pertains to a method and apparatus to provide for the display of characters and graphics in color. The invention includes three bit map memories which store graphics information for different colors, one character generator driven from a text memory for display of text, and an attribute memory for storing display characteristics such as inverse video and blinking. The contents of the bit map and attribute memories and the output of the character generator are used to address a pre-programmed ROM. The output from the ROM is a string of three bit words with each bit stream representing a primary color on a color CRT and being connected to the associated color input to the CRT. Composite graphics and text are displayed on the CRT.

Abstract: A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer system is such that one of the processors is allocated the bulk of memory band-width with the other processor taking the remainder. Arbitration for memory allocation is accomplished via a combination of a new firmware instruction and a semaphore.

Abstract: A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that particular character, utilizing a minimum of hardware. The loadable character generator of the invention replaces the ROM/PROM by a RAM utilizing 2K and 8 RAM memories, a 4K by 8 memory, 4 MUX chips, and a Motorola 6845 CRT Controller with various registers and is loaded through the attribute buffer.

Abstract: In combination with a multiprocessing/multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new call instruction architecture is implemented partly in firmware and partly in hardware. Also, a new stack mechanism stores hardware managed control information in a control frame and software controlled data in a data frame.

Abstract: A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/data bus, while a decoder permits the selection of one of the system devices during a microprocessor external operation in response to the most significant address bits. The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, information representative of the less significant address portion is latched. Datum information transfer to an output TTL gate is obtained by having an external operation executed by the microprocessor so that the most significant address bits select the gate and the less significant address portion represents the datum to be transferred.

Abstract: A needle end ruby of a needle printing head where the printing needle writing ends are arranged along one or more parallel columns is comprised of two or more plates juxtaposed on one or more planes. Each plate is rigidly fixed to the contiguous plate or plates. The ruby guiding openings for one column of the needle writing ends are obtained by shaping and grinding the sides along which two plates are juxtaposed and fixed.At least one of the plates comprising the ruby has a different height in relation to the remaining juxtaposed plate(s). Thus the ruby presents two ground surfaces used for accurately positioning the ruby into a housing in the nose end of a guiding needle head.Alternately the guiding ruby, though comprised of plates of equal height, can still present two reference ground surfaces by juxtaposing and fixing at least two of the plates in a staggered manner so as to expose precisely ground surfaces utilized to accurately position the ruby into its housing.

Abstract: A multicolor inked ribbon cartridge for an impact serial printer comprising a ribbon housing body and two arms protruding from such body to allow the interposition of a ribbon portion between a printing head and a printing support for the whole length of the platen when the cartridge is rotatably attached to the frame of an impact serial printer by means of two lateral cylindrically-shaped projections provided on the body of a cartridge thus permitting rotation of the body around a common axis of said cylindrical projections, parallel to the platen. The cartridge rotation around such axis and therefore the positioning of a suitable multicolor band between the printing head and printing support is assured by a cam actuated by a motor and interacting with the body of such cartridge. The cartridge is further provided with a string made tight between the ends of its arms upon the multicolor ribbon portion which is interposed between the head and printing support.

Abstract: An apparatus for decoding data wherein only binary ZEROs are received as electronic pulses, each pulse alternating in opposite directions and wherein binary ONEs require no pulse.The apparatus includes logic for receiving the negative and positive binary ZERO pulses, retiming the pulses and generating a positive pulse for each binary ZERO pulse. The positive pulse is retimed to a pair of complementary pulses and applied to a receiving device, typically a universal synchronous/asynchronous receiver transmitter (USART).

Abstract: An apparatus and a method is disclosed for correcting on-line error corrections in the digital transmission of voice or data utilizing forward error correction technique which avoids on-line calculations of the Massey or Berlekamp algorithms and the Chien search that it entails, and permits a simple hardware apparatus comprised of a ROM, shift registers, and exclusive OR gates, thus eliminating the requirement of a dedicated massive computer.

Abstract: The invention pertains to a computer display system for displaying text and graphics on a scan line basis wherein a scan line windowing apparatus for selectively blanking the graphics display is provided.A bit map memory, in addition to storing information to be displayed on a CRT, further stores a bit for each scan line which is utilized to control the enabling or disabling of a portion of the information in the bit map memory which is to be displayed on the CRT.

Abstract: A minicomputer system is disclosed having a bus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling an alternate route for issuing instructions from one processor to another. The logic detects information that is not to be transferred to the I/O devices and accordingly reroutes it back to the central processor and/or subprocessors.

Abstract: Computer modular housing with retractable stabilizers comprised of bearing feet shiftable relative to each other in a parallel direction, each of said bearing feet is independently movable laterally relative to the others so as to increase the frame bearing area and therefore increases the frame stability. They may also be retracted to a position which permits the assembly of modules against walls or other frames in order to form systems of juxtaposed modular units.

Abstract: A novel method and apparatus for latching and locking D-type electrical connectors. In one embodiment a novel "bud-stud" is utilized to replace prior art isoblocks or prior art hexagonal nuts. The bud-stud is capable of mating with either a prior art screw-type or spring-loaded latching arm to latch and lock the electrical connectors to each other and to a bulkhead.

Abstract: This invention pertains to a power FET control circuit which operates at higher switching frequencies for reducing the output voltage ripple. The control circuit provides two pulse control signals each shifted 180.degree. out of phase, each of such signals having a fixed frequency and a duty-cycle ratio which varies up to a maximum of 50%.

Abstract: A high definition page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character or graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line.