Abstract: The present invention relates to a memory cell, and more particularly to a single-bit, dual-port cell, and a single-sided read circuit for use with one or more such cells. The cell may, in one embodiment, be used in a static random access memory (RAM) array, and may be implemented in BICMOS technology on an integrated circuit. The cell has a flip-flop storage unit comprising a CMOS circuit of cross-coupled inverters coupled to dual CMOS pass gates to provide isolation and data transfer. The storage unit is also coupled to a bipolar read line driver in a particular configuration to accomplish rapid bit line pull-up or pulldown for high speed read operation. Several alternative embodiments are disclosed.