Abstract: An automated energy consulting system and method is provided comprising an interactive input system linked to calculation algorithms and databases of energy-related products and services, affiliated service providers, and climate, financing and regulatory criteria. The system generates proposals of available energy-related products, services and financing options, and obtains and aggregates customer commitments to allow discounted purchasing of the components. Customers can earn referral commissions to encourage customers and volunteers to virally disseminate the access information. For customers not eligible for beneficial products and services because of regulatory deficiencies, the system automates the customer education process to encourage them to advocate politically for the changes that will make them eligible.

Abstract: Disclosed is an Internet-based method that enables users to search and browse for information (such as price) about a plurality of items (such as books) available for sale on the Internet, compare prices for the items individually or considered as a package, and optimize the package price. In a preferred embodiment, the invention searches for the lowest price and second lowest price for the desired items from Internet Web sites and databases, records the data in two matrices, and employs algorithms that implement certain set operations, including Cartesian product and set union, to optimize the result for all items.

Abstract: Disclosed is an Internet-based sports equipment rental system and method that enables individuals to rent sports equipment and other items, such as golf clubs, from a renting company's Web site. The system and method includes automated rental processing and tracking software that runs on the renting company's Web site to allow individuals to rent sports equipment conveniently over the Internet for use at predetermined locations at predetermined future times.

Abstract: Disclosed is an inexpensive and easy-to-use multi-drawer storage cabinet and cabinet drawer retaining/locking system particularly well adapted for use with a mobile cabinet or a cabinet exposed to a shaking environment. The system has only one moving part, namely a rigid cage or frame positioned in front of the drawers and held in place by tracks mounted on either side of the cabinet. In an engaged position, the cage physically prevents the entire bank of drawers from opening, even if the entire cabinet is shaking or moving. In a disengaged position, the cage may be moved away from the drawers to permit the drawers to be opened through the cage while the cage remains mounted on the front of the cabinet for ease of later re-engagement. The retaining/locking system may be either built into a cabinet at the time of manufacture, or retrofitted to an existing cabinet.

Abstract: The present invention comprises a one-piece, lightweight shield for covering the top half of a person's forearm and the entire hand made into a fist clenched around a chisel or other tool. An opening is formed in the shield near the hand end to allow the tool to be grasped by the person's hand while wearing the shield. Straps are provided to attach the shield to the forearm. The shield may be made of shatter-resistant plastic or other durable, lightweight material.

Abstract: The disclosed facility type determination technique ascertains whether or not a facility connection is solely digital. In the disclosed embodiments, this information is used to establish the rate at which data is coupled through the facility connection. More specifically, a predetermined test signal including a pseudorandom sequence of digital signals is transmitted through the facility or combination of facilities connecting a data source to a data destination after the connection between the source and destination is established. The received test signal is examined at the destination and the examination results are used to determine the rate at which data is subsequently transmitted between the data source and data destination. Advantageously, this technique does not restrict network facility management and can be employed in a variety of data communication applications.

Abstract: A technique for use in communications systems utilizing busy and idle modes. In the busy mode, symbols representative of data are transmitted to system end users. In the idle mode, during which no data is communicated to end users, idle mode symbols are transmitted. Such idle mode symbols are not used to represent data and are only transmitted during the idle mode. Advantageously, such idle mode symbols maintain adaptive apparatus, such as AGC circuits, NEXT cancellers and equalizers, in their properly converged state. In the disclosed embodiment, the idle mode symbols are the innermost symbols in a signal constellation and transition from the idle to busy mode is represented by the transmission of a predetermined number of outermost symbols in the signal constellation. Use of such symbols for idle-to-busy mode transitions advantageously provides ready detection of such transitions. In addition, use of the innermost symbols for the idle mode reduces spectral emission and crosstalk.

Abstract: A bit decoder for a memory array includes a decode NOR/OR circuit coupled to an output driver circuit. The decode NOR/OR circuit includes a plurality of input signals connected to respective input FET's all of which are connected in parallel between a common source and a common drain node. One input is also connected to an active pullup FET which is connected in series with the input FET's at the common drain node and which is always maintained slightly on. A bipolar transistor pulls down the common drain node and a bleeder FET pulls down the common source node. The output driver is a BICMOS circuit that provides both the bit selection and bit refresh signals which are of opposite phase.

Abstract: A latch and driver circuit is disclosed for use in reading out data from a random access memory cell. The invention, which may be implemented in BICMOS technology, accomplishes high-speed asynchronous latching, level translation and output driving operations. The invention includes a latch and at least one output driver coupled in parallel to a latch driver.

Abstract: A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, . . . ) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g., CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one larger PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip.

Abstract: A receiver and level converter circuit is disclosed which may be used, for example, in converting low-level logic or other signals to high-level signals. In one embodiment, the circuit includes a differential amplifier having two feedback loops to provide an output signal having hysteresis, for increased gain, better noise margin and compensation. Each feedback loop includes a nonlinear difference network. In a preferred embodiment, the circuit is implemented in BICMOS technology, uses out-of-phase FETs as pull-down devices, and may be used to convert ECL-level signals to CMOS or BICMOS-level signals.

Abstract: The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration.

Abstract: A word decoder for a memory array includes a decode NOR/OR circuit 52 coupled to an output driver circuit 54. Decode NOR/OR circuit 52 includes a plurality of input signals IN1, IN2, IN3 connected to respective input n-channel field effect transistor (NEFTs) N1, N2, N3, all of which are parallel to a common node 1. The first input IN1 is also connected to a an active pull-up p-channel field effect transistor (PFETs) P1 which is in series with the first NFET N1 and always maintained slightly on. A bipolar transistor T4 pulls down node 1 and a pair of bleeder NFETs N4, N5 pull down nodes 3 and 2, respectively. Output driver circuit 54 is comprised of bipolar transistors T1, T2, T3 arranged in a push-pull configuration.

Abstract: According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15).

Abstract: The invention provides novel implementations of a latch cell in CMOS gate array technology to produce latch dissymmetry and permit a single ended data input. The dissymmetry is produced by increasing the output impedance of the second stage of the latch cell, which can be done, either in a DC or in an AC mode, or even in a mixed version of both modes.

Abstract: A transistor memory cell is disclosed of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data. The cell is equipped with controlled active devices for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. Each active device is characterized with a forward low-impedance current direction and reverse high impedance current direction therethrough for each saturation transistor. Each active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, each active device discharges to a word line when the line is brought to an appropriate control potential. In another embodiment, each active device discharges to a separate discharge line not connected to the work line when the former line is brought to an appropriate control potential. The active devices may be diodes.

Abstract: The present invention relates to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A 3 way OR/NOR circuit of this invention includes a standard differential amplifier, the first branch of which is controlled by logic input signals. The second branch includes a current switch controlled by a reference voltage. The differential amplifier provides first and second output signals simultaneously and complementary each other. The circuit further includes two push pull output buffers. The first output buffer comprises an active pull up device connected in series with an active pull down device, and the first circuit output signal is available at their common node or at the output terminal.

Abstract: A current switch emitter-follower logic circuit allows both the UP output logic level and the DOWN output logic level to be independently controlled with respect to a fixed reference voltage so as to permit very small output level swings. A feedback circuit generates two different control signals which are independently variable and are input to a control circuit and to a logic circuit to compensate for fluctuations in power supply voltages, temperature and circuit parameters. These control signals are applied to a variable current source within the logic circuit and to a dynamic resistance within the control circuit to compensate almost instantaneously to fluctuations in power supply voltage, temperature or circuit device parameters, maintaining the logic circuit output levels close to reference levels so as to permit small output signal swings. The output logic levels need not be symmetrical around a central reference point.

Abstract: Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls.In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lighography, per se, is formed.

Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.