Abstract: A method of relieving timing-based congestion during physical implementation of a programmable logic device can include routing a placed circuit design for the programmable logic device in a delay mode and calculating an initial delay for connections of the circuit design based upon the routing step. A final delay for connections of the circuit design can be predicted with connection sharing removed. Connections of the circuit design that do not conform with timing constraints based upon at least one of the initial delays or the final delays can be identified. Accordingly, a detailed routing of the circuit design or further optimization of the circuit design can be selectively performed according to the determination regarding the timing constraints.

Abstract: A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modules can be floorplanned thereby determining a placement solution that does not violate boundaries of unchanged modules. The programmable logic device then can be placed and routed.

Abstract: A method (200) of placing inputs, outputs, and clocks in a circuit design can include assigning (205) initial locations to inputs and outputs of the circuit design, selecting (210) at least one component type for the circuit design, and generating (215) a cost function having parameters corresponding to the selected component type. The method further can include annealing (220) the selected component type using the cost function and determining design constraints (225) for the selected component type according to the annealing step. The method can repeat to process additional component types such that design constraints determined for each additional component type do not violate design constraints determined for prior component types.

Abstract: A method of estimating congestion for a programmable logic device can include calculating a number of fan-in paths for each resource in the programmable logic device and calculating a number of fan-out paths for each resource in the programmable logic device. For each resource of the programmable logic device, a number of paths having different path characteristics can be determined and a probability can be assigned thereto. One or more measures of congestion can be computed according to the determining step.

Abstract: A method of implementing a user integrated circuit (IC) design in a tree representation includes the step of introducing the tree representation for the user IC design in a partitioned manner including at least one sub-design to form a design abstraction of the user design. At least one sub-design can include a sub-design providing for multiple levels of implementation hierarchy. The method can further include the step of traversing the design abstraction in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for at least one sub-design, and the step of traversing the design abstraction in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs. Traversing the design abstraction in the bottom-up fashion can facilitate a re-budgeting of timing for the integrated circuit design.

Abstract: A method of designing an integrated circuit using a general purpose programming language can include identifying a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined and access to the modeled global memory can be scheduled. The programmatic design can be translated into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.

Abstract: The invention provides a method for annotating a computer program. Program code for the computer program can be displayed in a user interface (100) having a code display window (105). One or more elements of the displayed program code can be linked to a data file (120) having one or more implementation instructions for elements of the computer program. In response to a query initiated by selecting one of the linked elements (157), a corresponding implementation instruction for the queried element can be displayed in an implementation display window (115) of the user interface.

Abstract: A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction function using a half-word literal field in an instruction word that impacts a whole word logically through a combination of modes that variously manipulates the distribution of a set of literal bits of the half-word literal field across the instruction word.

Abstract: A method (100) of physical circuit design can include the steps of packing components (110) of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations (115) to each component of the circuit design. The components of the circuit design can be clustered (120) by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed (125) to minimize critical connections. The circuit design can be declustered (130) to perform additional placer optimization tasks (135) on the declustered circuit design.

Abstract: A flexible architecture for nesting joint test action group (JTAG) test access port (TAP) controllers for FPGA-based embedded system-on-chip (SoC) is provided. Advantageously, a programmable approach permits bits in a selectable bit register (302) to be selected based on the number of JTAG TAPs that will be utilized. The selected bits can be used to vary the apparent length of an instruction register (302). Importantly, the flexible architecture permits access to any combination of a plurality of JTAG TAP controllers in the FPGA-based embedded SoC without the need to rewire any I/O pins of the FPGA and/or embedded IP cores.

Abstract: A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (100) and identifying data input to each component specified in the language independent model to determine a latency for each component (220, 225). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (230). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself (235).

Abstract: A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language (100) and identifying a loop construct within the language independent model (705). A determination can be made as to whether the loop construct is bounded (725). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences 735). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique (740, 755).

Abstract: A flexible architecture for extending the instruction set for a boundary-scan interface. An instruction can be selected from a memory store (308) and decoded by a decoder (310). The instruction can subsequently be shifted into an instruction register (349) where it can be executed. Alternatively, a length of an existing instruction register (382) of a boundary-scan interface can be programmably appended to effectively increase the length of the register. A plurality of serially arranged bit registers (376, 378, 380) can be connected in series with the existing instruction register. By selecting an outer one of the serially arranged bit registers, the length of the existing instruction register can be extended.

Abstract: As system components which are used to customize an FPGA-based embedded processor SoC are selected and configured, the actual or estimated resources can be immediately provided. A GUI (350) can facilitate display of resources utilized by any or all selected system components, resources available for use by unselected system components and the customized device resources. Resource conflict and configuration checks can be used to identify and resolve system component problems and design and specification requirements. Notably, any associated resource problems can be immediately identified and rectified.

Abstract: Within a computer automated tool, a method (400) of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying (405) a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining (410) an initial routing of the clock domain. The method also can include determining (420) a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (430). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode (455) allowing sharing of routing resources by different nets.

Abstract: A system (20) for dynamic reconfigurable computing includes at least one microprocessor implemented on a field programmable gate array (10) having a programmable fabric (12). The system can include a predefined interface (42) between an embedded microprocessor and the programmable fabric as well as a translator (25) enabling a single hardware description language to define the system including both the microprocessor and the programmable fabric.

Abstract: During a reset condition or prior to system initialization of an FPGA-based system (100), a FPGA (102) can be pre-configured by loading a value from a memory cell (108) into at least one flip-flop (312) of the FPGA, which represents a configuration register for an FPGA memory controller (106). The FPGA memory controller can be configured using the value loaded in the flip-flop. The value loaded into the flip-flop from the memory cell can be a default value previously stored in the memory cell.

Abstract: A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (105, 110, and 115). The language independent model can be scheduled such that each component is activated when both control and valid data arrive at the component (120). An interface structure specifying a hardware interface through which devices external to the language independent model interact with a physical implementation of the language independent model can be defined and included in the language independent model (200, 300, 400).

Abstract: The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component (380) used for customizing the FPGA-based SoC can be configured (382) using parameters that can be automatically propagated (384) and used to configure peer system components. During configuration (388) of the peer system components, other parameters used to configure those peer system components can also be propagated (400) and used to configure other system components during customization of the FPGA-based SoC.

Abstract: A method (300) of generating a simplified netlist using bus information includes the steps of identifying (302) nets that form buses in a netlist and identifying (304) instances of a same type that connect to the identified nets via pins of the same name to form at least one set of instances. The method further includes the step of replacing (308) at least one set of instances with at least a single arrayed instance if each net in a bus is connected to exactly one of the same type of instance via a pin of the same name and the step of deleting the nets forming the arrayed instance from the netlist and replacing (314) the nets with a corresponding bus.