Abstract: One embodiment of the present invention provides a system that hierarchically groups principals to facilitate collision warning. During operation, the system obtains information on a number of principals and constructs one or more first-level groups of principals. Within a first-level group, the system constructs one or more second-level groups, thereby facilitating an assessment of probability of collision between a second-level group and a primary principal.

Abstract: Embodiments of a system, a method, and a computer-program product (e.g., software) for aggregating an energy service from a group of loads with time-varying operating cycles are described. This aggregation may be performed by an aggregator, which provides the energy service to a power-system operator. In particular, for a desired demand response, a demand-response mechanism may modify a demand response of a given load by mapping an initial operating cycle of the load before a demand-response event to a final operating cycle. In addition, the demand-response mechanism may transition the given load to a new operating cycle associated with the demand-response event using a temporal set-point trajectory. This aggregation technique may ensure that a distribution of phases of the group of loads is, on average, uncorrelated with each other, either by preserving or modifying the distribution of phases prior to the demand-response event.

Abstract: A cooling mechanism includes a first heat exchanger, a first fluid-flow port, and a second fluid-flow port. The first heat exchanger includes a forced-fluid driver and is configured to pump heat from inside an enclosed area to outside of the enclosed area. Furthermore, the first fluid-flow port is configured to accommodate a first fluid flow into the enclosed area and the second fluid-flow port is configured to accommodate a second fluid flow from the enclosed area. Note that the first fluid-flow port and the second fluid-flow port are approximately coplanar. In addition, a given fluid-flow port, which may be either or both of the fluid-flow ports, is tapered to have an associated cross-sectional area which is smaller at an edge of the given fluid-flow port that is proximate to the outside of the enclosed area than at an edge of the given fluid-flow port that is proximate to the inside of the enclosed area.

Abstract: Embodiments of a system that includes an array of chip modules (CMs) is described. In this system, a given CM in the array includes a semiconductor die that is configured to communicate data signals with one or more adjacent CMs through electromagnetic proximity communication using proximity connectors. Note that the proximity connectors are proximate to a surface of the semiconductor die. Moreover, the given CM is configured to communicate optical signals with other CMs through an optical signal path using optical communication, and the optical signals are encoded using wavelength-division multiplexing (WDM).

Abstract: One embodiment of the present invention provides a system that trains a pattern-recognition model for electronic prognostication for a computer system. First, the system monitors a performance parameter from a set of computer systems that includes at least two computer systems, wherein monitoring the performance parameter includes systematically monitoring and recording performance parameters in a set of performance parameters from computer systems in the set of computer systems, wherein the recording process keeps track of the temporal relationships between events in different performance parameters in the set of performance parameters. Next, the system generates a training data set based on the monitored performance parameter from the set of computer systems, wherein generating the training data set includes concatenating two or more time-series of the performance parameter from computer systems in the set of computer systems.

Abstract: Some embodiments of the present invention provide a system that executes an application. During operation, the system physiologically monitors a user of the application with a set of sensors as the application executes. Next, the system assesses a mental state of the user based on physiological data collected from the sensors. Finally, the system changes the behavior of the application based on the assessed mental state to facilitate use of the application by the user.

Abstract: A system, method and graphical user interface for focusing a view of displayed data upon a subset of the data. In a view of multiple values, fields, objects or other data, a subset of the data is selected because it has changed, because it is associated with a recommended action, because it warrants a user's attention, or for some other reason. The remaining data is then masked or covered with a semi-transparent layer that suppresses the data and obscures any highlighting, emphasis or other complexity among the covered data. The user's attention is thus focused upon the selected subset of data without increasing the cognitive load forced on the user.

Abstract: One embodiment of the present invention provides a system for predicting a remaining useful life (RUL) for a component in a set of components within a computer system. The system starts by collecting values of at least one degradation-related parameter associated with the operation of a monitored component within the computer system. Note that the degradation-related parameter is a direct measurement of a degree of degradation of the monitored component. The system additionally collects values of at least one stress-based parameter from the computer system. Note that the stress-based parameter measures an accumulative stress in the operating environment of the set of components which can cause degradation of the set of components. The system then uses the values of the at least one degradation-related parameter and the values of the at least one stress-based parameter to predict an RUL for a component in the set of components.

Abstract: One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values.

Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.

Abstract: A device such as a multicolor light emitting diode that emits different colors of light and that may combine the different colors emitted by individual light emitting diodes. The multicolor LED may include a common anode terminal that may be connected to each anode of the individual light emitting diodes. The multicolor LED may be a five terminal multicolor LED. Additionally, the multicolor LED may include two anode terminals, in which the first anode terminal may be a common anode terminal connected to three of the individual color LEDs and the second anode terminal may be connected to an anode of a white LED. In this embodiment, the multicolor LED may be a six terminal multicolor LED.

Abstract: Snapshots of data and metadata associated with the data are created. The snapshot of the data is separate from the snapshot of the associated metadata. The snapshot of metadata is maintained locally in a cloud network attached storage (NAS) and globally. The snapshot of data is maintained according to an accessibility metric. Snapshot of metadata is transmitted from a backup remote site to a cloud network attached storage (NAS). A request for data corresponding to the metadata is received from the cloud NAS. The requested data is not available at the cloud NAS. The requested data is transmitted from the backup site to the cloud NAS.

Abstract: One embodiment of the present invention provides a system that non-intrusively detects counterfeit components in a target computer system. During operation, the system collects target electromagnetic interference (EMI) signals generated by the target computer system using one or more antennas positioned in close proximity to the target computer system. The system then generates a target EMI fingerprint for the target computer system from the target EMI signals. Next, the system compares the target EMI fingerprint against a reference EMI fingerprint to determine whether the target computer system contains a counterfeit component.

Abstract: An integrated circuit that includes an optical waveguide to convey an optical signal via an optical mode in an on-chip optical waveguide is described. In this integrated circuit, a cross-sectional area of the optical waveguide may be tapered in proximity to an electro-optic modulator in the integrated circuit, such as a germanium electro-optic modulator or a quantum-well (QW) electro-optic modulator. In particular, the cross-sectional area may be tapered from a first diameter distal from the electro-optic modulator to a second diameter proximate to the electro-optic modulator. This so-called ‘inverse taper’ may increase the spatial extent or size of the optical mode, thereby allowing the optical signal to be optically coupled to or from the electro-optic modulator with low optical loss.

Abstract: One embodiment provides a system that pre-fetches into a sibling cache. During operation, a first thread executes in a first processor core associated with a first cache, while a second thread associated with the first thread simultaneously executes in a second processor core associated with a second cache. During execution, the second thread encounters an instruction that triggers a request to a lower-level cache which is shared by the first cache and the second cache. The system responds to this request by directing a load fill which returns from the lower-level cache in response to the request to the first cache, thereby reducing cache misses for the first thread.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.

Abstract: A system that provides error detection and correction for a memory that has a specific failed memory component accesses a block of data from the memory. Each block of data includes an array of bits logically organized into rows and columns, including a column including row-checkbits, a column including inner checkbits and data bits, and columns containing data bits. Each column is stored in a different memory component and the checkbits are generated from the data bits. Next, the system attempts to correct a column of the block by using the checkbits and the data bits to produce a corrected column. The system then regenerates row-parity bits and the inner checkbits for the block of data, wherein the block includes the corrected column, and compares the regenerated row-parity bits and inner checkbits with existing row-parity bits and inner checkbits.

Abstract: Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation.

Abstract: A memory system accesses a block of data, each block including bits logically divided into rows and columns, each column including a row-checkbit column, an inner-checkbit column, and data-bit columns. Each column is stored in a different memory component, and checkbits are generated from databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. The system calculates a row syndrome and an inner syndrome for the block of data, the inner syndrome resulting from any two-bit error in the same row being unique. The system can use the row and inner syndromes to determine whether errors are associated with a failed memory component. If not, the system can use the row and inner syndromes, and inner syndromes for all possible combinations of one-bit errors occurring in two rows with a row syndrome of one to correct two bits.