Abstract: A method for programming complex programmable logic devices (CPLDs) to implement a logic function, whereby user-designated locked equations of the logic function are mapped into the macrocells of a function block, and then undesignated (non-locked) equations are mapped into the remaining macrocells. The method shifts product terms between the macrocells to adjust the placement arrangement of the mapped equations, thereby obtaining a placement arrangement which is both valid and meets user-defined timing constraints.

Abstract: A post-placement residual overlap removal process for use with core-based programmable logic device programming methods that is called when an optimal placement solution includes one or more overlapping cores. Horizontal and vertical constraint graphs are utilized to mathematically define the two-dimensional positional relationship between the cores of the infeasible placement solution in two separate one-dimensional (i.e., horizontal and vertical) directions. Next, the constraint graphs are analyzed to determine whether they include a feasible solution (i.e., whether the overlaps existing in the placement solution can be removed simply by reallocating available resources to the overlapping cores). If one of the constraint graphs is not feasible, then the infeasible constraint graph is revised, and then the feasibility of both graphs is re-analyzed for feasibility. The feasibility analysis and constraint graph revision steps are repeated until both constraint graphs are feasible.

Abstract: A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus line is programmably connected to a plurality of I/O lines via programmable interconnect points (PIPs). At least two of the second lines are connected to the input terminal of each flip-flop via portions (e.g., multiplexers) of the mode control circuit. Programming the PIPs to link selected flip-flop input and output terminals forms one or more shift registers of a selected length.

Abstract: A method for controlling power consumption and output slew rate in a programmable logic device, which is programmable to emulate a user-defined logic function. After placing and routing the user-defined logic function such that a plurality of paths are assigned to associated resources of the programmable logic device, a group of the resources associated with at least one path of the logic function which is constrained by a user-defined timing specification is identified. These resources are sorted according to their respective power consumption. A first sub-group of the resources is then identified which, when operated in a low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of all paths.

Abstract: A programmable input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal, the I/O circuit including a pull-up transistor, a gate bias control circuit and a well bias control circuit, all being connected between Vcc and the I/O terminal. The gate bias control circuit connects the gate of the pull-up transistor to the I/O terminal and the well bias control circuit connects the bulk terminal of the pull-up transistor to the I/O terminal when the I/O circuit is in a 5V tolerant input mode. The gate bias control circuit connects the gate of the pull-up transistor to the system voltage source and the well bias control circuit connects the bulk terminal of the pull-up transistor to Vcc when the I/O circuit is in a PCI compliant input mode. In an output mode, the gate bias control circuit and well bias control circuit allow the pull-up transistor to pull up the I/O terminal to Vcc in response to a pull-up data signal.

Abstract: In a renewing apparatus, a thermal transfer recording medium is made to be used plural times by simple configuration although such a recording medium must be thrown away in the prior art, and the running cost in the printing can be significantly reduced. The apparatus has coating means for applying a thermal transfer recording material including at least one of a photopolymerizing monomer and a photopolymerizing polymer and a coloring agent to a substrate, means for sending the thermal transfer recording medium and means for irradiating light onto the recording material.

Abstract: A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both "fast" function blocks (FFBs) and "high density" function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.

Abstract: An electrostatic discharge (ESD) protection circuit for an IC device including a triple-well SCR and a control circuit connected between the triple-well SCR and ground. The triple-well SCR is implemented using triple-well CMOS technology to facilitate connection of the control circuit by isolating both terminals of the triple-well SCR from ground. The control circuit includes a switch circuit, a capacitor, or a combination thereof, for controlling the holding voltage of the triple-well SCR. The switch circuit is closed during non-operation (i.e., before power is applied to the IC device protected by the SCR) so that electrostatic discharge (ESD) energy is transmitted to ground through the triple-well SCR. Similarly, the capacitor transmits ESD pulses to ground during ESD events. During normal operation of the IC device, the switch circuit is controlled by system voltage to remain open.

Abstract: An apparatus and method for testing ball grid array integrated circuits (BGA ICs) including a nesting member resiliently supported on a contactor body via guide shafts. The nesting member includes alignment walls and an alignment plate defining chamfered through-holes. The alignment wall is slanted to provide rough alignment of the IC within the nesting member, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Spring-loaded pogo pins are mounted on a circuit board and have pointed tips extending toward a lower surface of the nesting member alignment plate. When the nesting member is pushed toward the circuit board by a device handler, the pointed tips of the pogo pins extend through the through-holes and pierce the solder balls of the IC, thereby providing electrical contact between the IC and the interface apparatus.

Abstract: A method for programming PLDs in which feedback signals are alternately programmed to produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by multiple concurrent switching events. The method is applied to CPLDs having interconnect matrices including input lines and output lines connected by programmable connection circuits, and having macrocells connected at their output to one of the input lines via first selective inversion circuits, and connected at their input to the output lines via second selective inversion circuits.

Abstract: An interface structure for providing connections between integrated circuit (IC) devices and a device tester. The interface structure includes a printed circuit board having one or more groups of pogo pins, each group being arranged to contact the pins extending from the pin grid array package of one IC device, and includes interconnect paths from the pogo pins and the device tester. The groups of pogo pins are mounted directly into the printed circuit board in a universal footprint arrangement that is customized to receive a plurality of different pin grid array package footprints. A nonconductive cover plate is mounted over the pogo pin groups upon which the IC devices are mounted by a handler. A mother board is connected between the printed circuit board and the device tester.

Abstract: An improved arithmetic logic unit (ALU) of an erasable-programmable logic device (EPLD) with a flexible, programmable carry function allows a broad range of functions to be implemented. The inventive circuit utilizes a separately configurable carry chain with multiple logic and arithmetic function capabilities.

Abstract: A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage.

Abstract: A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor.

Abstract: The present invention relates to a head transferring mechanism of a magnetic recording/reproducing apparatus which transfers a magnetic head. In the head transferring mechanism 17 in which a hold case 19 is hinge-connected to a rear end portion of a carriage 18, a fitting bed 18p is formed on a central portion of the tip portion of the carriage 18 and an adhesive filling groove 18r and a clearance groove 18s are made in an upper surface of the fitting bed 18p to be close to each other. Further, after a lower magnetic head 20 is placed on the fitting bed 18p, a lower surface of the lower magnetic head 20 is adhered and fixed onto the fitting bed 18p through an adhesive 28 put in the adhesive filling groove 18r.

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship.

Abstract: A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.

Abstract: A method for placing a logic function into the function blocks of a complex programmable logic device (CPLD) to maintain the same input/output pin locations after the logic function is subsequently modified by a user. The method utilizes a weighting function to assign portions of the logic function to the function blocks such that sufficient resources are available in each function block to implement subsequent modifications to the logic function without changing the originally-assigned input and output pin locations. For each portion of the logic function, the weighting function is employed to identify the function block which implements the portion while maximizing the available resources in all of the function blocks. If a particular equation cannot be placed, the method utilizes a corrective measure such as fitting refinement, buffering and logic reformation to place the equation.

Abstract: A fine particle dispersing apparatus including a cylindrical body, a funnel nozzle provided at the bottom of the cylindrical body, and a valve having a clearance forming member forming a clearance with the inner wall of the funnel nozzle which is larger than the diameter of the fine particles. The funnel nozzle and/or the clearance forming member oscillates, thereby causing the fine particles present within the funnel nozzle to pass through the clearance and discharge from the nose portion of the funnel nozzle.

Abstract: An interface assembly in the present invention includes a plate for mounting a test head, a plurality of alignment pins for aligning the test head to a device including a plurality of compressible pins, and a plurality of vacuum-activated components for coupling the plate to the device. After the test head is positioned in operative relation to the other device, the vacuum-activated components provide a vacuum which draws the plate and the device together. The interface assembly eliminates the purely mechanical securing of the plate to the device, thereby minimizing any rocking of the test head and ensuring equal compression of the plurality of compressible pins. The interface assembly also ensures safe user operation by providing that any obstacle (such as a user's finger) between the interface assembly and the device prevents creation of a vacuum. Thus, the present invention provides a time-efficient, reliable, safety-conscious means for positioning a test head relative to another device.