Abstract: A device, system and method for aligning data received on a plurality of data lanes in a data link are disclosed. One or more alignment vectors are generated for each of a plurality of data lanes where each alignment vector represents a location of an alignment character in an associated one of the data lanes. For each data lane, a plurality of alignment vectors may be associated with one or more alignment windows associated with the data lane. If the alignment vectors of the data lanes are associated with a common alignment window, an alignment position may be selected for each data lane.

Abstract: Disclosed is a transimpedance amplifier comprising a multistage amplifier and a feedback circuit coupled between a single ended input terminal and one of a plurality of differential output terminals of the multistage amplifier. The feedback circuit may control an input voltage at the single input terminal to substantially maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

Abstract: Described are a circuit and system to provide an output signal in response to composite input signal comprising an AC signal component and a DC signal component. An amplifier provides an amplified voltage signal in response to a voltage representative of the composite signal. A filter may provide a filtered voltage signal having a magnitude that is representative of a magnitude of the DC signal component in response to the amplified voltage signal. A DC signal removal circuit may substantially remove at least a portion of the DC signal component from an input terminal in response filtered voltage signal.

Abstract: Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.

Abstract: Disclosed is a transimpedance amplifier comprising a multi-stage amplifier, a DC current detection circuit to detect a DC current component of an input signal and a DC current removal circuit to substantially remove the DC current component of the input signal.

Abstract: Disclosed are a system and method of configuring processing resources for communication with one or more devices coupled to a data bus through a bridge. Resources at a processing system may be configured to communicate with the bridge as a transparent bridge or a non-transparent bridge depending on how the processing system may be implemented in a processing platform.

Abstract: A laser driver circuit to provide a modulation current is disclosed. A current mirror circuit generates the modulation current in response to a reference current. The current mirror circuit comprises an operational amplifier providing an output signal to gates of transistors forming the current mirror circuit.

Abstract: Disclosed are a system and method of transmitting and receiving data through a peripheral device coupled to a transmission medium. The peripheral device is coupled to a host processing system through a data bus. The peripheral device includes logic to discriminate among data cells based upon virtual channels and maintains a receive buffer for storing data cells for each virtual channel. When a buffer fills, the peripheral device transmits the data cells to a receive buffer queue associated with a virtual channel and maintained in the host processing system. The host processing system may also maintain a plurality of transmit buffer queues for storing data cells for transmission in virtual channels. The peripheral device may also comprise logic for scheduling data cells in the transmit buffer queues for transmission according a quality of service (QoS) associated with one or more virtual channels.

Abstract: Disclosed are a system and method of transmitting data in a processing platform. A switch may comprise an upstream port coupled to a root device to communicate with a processing system. The switch may also comprise a plurality of downstream ports where each downstream port is adapted to be coupled to a device. Data may be transmitted between downstream ports based upon routing information for transmitting data from the upstream port to each of the downstream ports.