Abstract: Certain non-limiting exemplary embodiments are taught which include a game comprising, a digital processor, digital storage coupled to the digital processor for storing instructions, a display coupled to the digital processor displaying a first plurality of indicia arranged in a plurality of rows and a plurality of columns such that there are a plurality of paylines through a contiguous plurality of indicia, a user interface coupled to the digital processor to select a subset of the first plurality of indicia taken along at least one column and to initiate a display of a second plurality of indicia which includes the selected subset of the first plurality of indicia on the display, and an award dispenser providing an award which is at least as large as the largest award associated with the plurality of paylines.

Abstract: A getter system for plasma flat panel displays is disclosed. In a plasma flat panel display having front and rear panels sealingly joined together at peripheral edges thereof to define an inner space and a plurality of walls disposed within the inner space, the walls defining a series of substantially parallel secondary channels with openings at first and second ends thereof and a main channel extending along the perimeter of the front and rear panels, the getter system includes at least one nonevaporable getter device disposed within the inner space. The at least one nonevaporable getter device may be located in a portion of the main channel that faces the openings at one of the first and second ends of the secondary channels.

Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

Abstract: A digital integrated circuit provided with a dual latch clocked LSSD that includes a master latch coupled to a slave latch such that it operates in at least three operational modes. Preferably the three modes of the dual latch clocked LSSD include a functional mode, a capture mode, and a shift mode. In the functional mode, the dual latch clocked LSSD operates as an edge-triggered flip-flop storage element. In the capture mode, the dual latch clocked LSSD operates as a level sensitive latch storage element controlled by the system clock, one of two scan clock signals, and, preferably, by a test mode input signal. In the shift mode, the dual latch clocked LSSD again operates as a level sensitive latch storage element, but is controlled by a pair of shift clocks. By separating the capture mode from the functional mode, the dual latch clocked LSSD is exceptionally resistant to skew problems in both the capture and the shift modes.

Abstract: Method and apparatus for connecting an I/O pad of an integrated circuit die to an electrical lead or contact on a lead frame that uses interposers formed directly on the die attach pad of the lead frame. Each interposer is formed by etching one or more grooves, preferably of depth no more than half the die attach pad thickness, in the die attach pad adjacent to the lead frame electrical lead(s). The exposed surfaces of the grooves and the die attach pad are coated with a layer of electrically insulating material, and the grooves are then filled with an electrically conducting material, such as conductive epoxy. An electrically conducting wire is then bonded between an I/O pad of an integrated circuit die and the electrically conducting material in the groove, and between the electrically conducting material and an electrical lead of a lead frame.

Abstract: A method for making a self-supporting porous semiconductor membrane characterized by the electrolytic etching of a surface of a semiconductor wafer until at least one pore propagates fully through the wafer. The wafer forms the anode of the cell and a relatively inert material, such as platinum, forms the cathode of the cell. The electrolyte is a mixture of HF, H.sub.2 O and possibly a wetting agent. One side of the semiconductor wafer is shielded from the electrolyte and pores are allowed to propagate through the body of the wafer towards the shielded side. In one embodiment of the invention the pores are allowed to propagate fully through the body of the wafer and in another embodiment the pores are partially propagated through the wafer and then material is removed from the shielded side of the wafer to expose the pores.

Abstract: A hand-held wrench having a mechanism for automatically feeding a fastener into its driving tip. The wrench includes a hollow handle portion enclosing a spring-loaded shaft which biases a number of fasteners disposed within a driver portion towards the driving tip of the wrench. A detent mechanism is provided to hold the fasteners at the driving tip until the fastener driving operation is completed.