Abstract: A method of pruning an initial timing graph for static optimization of a digital circuit includes examining a first group of nodes, which in turn include at least a first one of the nodes in the initial timing graph, to determine whether every node in the first group is prunable. The method further includes pruning the first group by pruning every node therein, if every node therein is prunable, and if the pruning would be beneficial. Furthermore, the method includes repeating the examining and pruning steps for a substantial number of additional groups of nodes, so as to create a pruned timing graph having enhanced numerical qualities and/or compactness compared to an initial timing graph. The pruning can be conducted on groups of more than one node at a time, or on only individual nodes at one time.

Abstract: A connector for a portable device, includes a jack portion integral to the portable device, and a plug portion attached to an input/output device for being inserted into the jack portion. The connector is preferably a low cost microwave connector for transmitting multiple signal types and provides dual functionability.

Abstract: The boxed-in slot antenna is provided with a conductive box, functioning as a waveguide, which is configured substantially parallel to the ground plane in which the slot is formed, thereby providing significant space savings relative to prior art designs wherein the box is positioned perpendicular to the conductive ground plane. The inventive antenna can be easily constructed using printed circuit board technology, by forming the ground plane as a coating on one side of a printed circuit board substrate, forming the main conductive plane of the conductive box structure on the other side of the printed circuit board, and interconnecting the two using plated through holes (that is, vias). The folded structure of the conductive box of the present invention makes it particularly suited for space-critical applications, such as may be found in laptop computers and other portable and handheld electronic devices, which it is desired to interconnect with a wireless local area network (wireless LAN).

Abstract: A system and method for determining the location of a particular device on an integrated circuit chip is described. The system and method utilize apparatus for detecting the emission of light during switching events of devices in the circuit during the circuit's processing of an input calculated to actuate the device whose location is desired. Light emissions from the circuit can be temporally and spatially indexed so as to allow deduction, in combination with the a priori knowledge of the logical operation of the circuit, of the location of the desired element. In another embodiment of the invention, a series of images of the circuit can be accumulated, representing the circuit's response to a series of different input signals, each input signal being designed to result in the switching of the desired element. The series of images can be compared to determine the location of the desired element.

Abstract: The LC VCO includes an LC oscillator module with first and second tank nodes and a control module with positive and negative input voltage terminals. The control module includes four voltage dependent capacitive elements which are configured to be biased for operation as voltage dependent variable capacitances. The voltage dependent capacitive elements are interconnected such that the effect of a common mode input voltage is to increase the capacitance of two of the voltage dependent capacitive elements, while simultaneously decreasing the capacitance of two of the other voltage dependent capacitive elements by a substantially similar amount, such that a differential voltage applied across the positive and negative input voltage terminals is operable to change the capacitance of the voltage dependent capacitive elements, and thereby the frequency of the LC oscillator module, while effects on the output frequency of the oscillator caused by a common mode voltage tend to cancel.

Abstract: A method of, and apparatus for, operating an automatic message recognition system. In accordance with the method the following steps are executed: a user's speech is converted to a first signal; a user's handwriting is converted to a second signal; and the first signal and the second signal are processed to decode a consistent message, conveyed separately by the first signal and by the second signal, or conveyed jointly by the first signal and the second signal. The step of processing includes the steps of converting the first signal into a plurality of first multi-dimensional vectors and converting the second signal into a plurality of second multi-dimensional vectors. For a system employing a combined use of speech and handwriting the step of processing includes a further step of combining individual ones of the plurality of first multi-dimensional vectors and individual ones of the plurality of second multi-dimensional vectors to form a plurality of third multi-dimensional vectors.

Abstract: A dynamic incrementer, implemented in the Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS) circuit family, which internally performs single rail calculations and which generates the dual rail result using a strobing technique. The carry-lookahead function is implemented with an OR tree using the complement input signals, resulting in a very fast and economical incrementer.

Abstract: Tracing a short as a shortest path of explicit VLSI design component instances between two VLSI design component instances with different net names in a hierarchical design is a non-hierarchical problem. The method described in this document computes a shortest path of VLSI design leaf component instances containing at least one of the leaf design components causing the sort. To avoid exceeding available storage, the non-hierarchical instance information maintained during the process is pruned optimally. To achieve feasible performance, two methods to find “good” starting points are provided, based on geometrical distribution or based on connectivity information from the net build (if available).

Abstract: Tracing a short as a shortest path of explicit Very Large Scale Integrated (VLSI) circuit design component instances between two VLSI design component instances with different net names in a hierarchical design is a non-hierarchical problem. The method described in this document computes an approximation for the shortest path of VLSI design component instances taking full advantage of the hierarchical structure of the design. For the resulting path it is guaranteed that it contains at least one of the VLSI design component instances that cause the short. For each individual cell a Shortest Path Search (SPS) can be applied. In comparison to prior flat searches, which required unfeasible amounts of storage and computation time on large nets, this solution requires asymptotically not more storage and computation time than other forms of hierarchical VLSI checking tasks.

Abstract: Real time digitization of handwritten text and integration of digital recordation of handwritten text with traditional paper-based record making systems is achieved with a recording unit which may record a sequential data stream of strokes and associated events. The data stream may be stored in the apparatus and processed in accordance with various applications. Recordation of handwritten strokes may be accompanied by automatic detection and recordation of predefined events, and by user invoked generation of events. Recorded handwritten text may be processed to produce character strings or image data for text recorded in conjunction with predefined events.

Abstract: A speech recognition apparatus and the method thereof for correctly recognizing an English word from a non-native English pronunciation, for example. A vector data generating part and a label generating part processes speech data of a sentence of English speech pronounced by a Japanese speaker to convert it to a label string. A candidate word generating part correlates the label string of the sentence to a first candidate word comprising one or more English words. An analogous word adding part uses a word database to search an English word analogous the pronunciation of the first candidate word, such as a analogous word “lead” for a first candidate word “read”, for example, (it is difficult for a Japanese speaker to discriminate between “l” and “r” in pronunciation), and adds the obtained analogous word to the first candidate word to make it be a second candidate word.

Abstract: A modified inverted-F antenna is disclosed that improves on conventional designs by incorporating a sloped grounding element at a fixed end of the horizontal element and a downward bend at a loose end of the horizontal element. The sloped grounding element is connected in a triangular configuration with the feeding element and a ground plane of the antenna, to provide additional benefits. The triangular shape of the present invention decreases the distance, D, between the grounding plane and the feeding element relative to a conventional rectangular connection. The triangular shape also provides increased mechanical strength relative to a conventional rectangular connection. The downward bend at the loose end of the antenna can be adjusted to thereby further adjust the impedance matching of the antenna. The sloped grounding element and downward bend features of the modified inverted-F antenna also serve to reduce the overall dimension of the antenna.

Abstract: Methods and apparatus for performing speaker recognition comprise processing a video signal associated with an arbitrary content video source and processing an audio signal associated with the video signal. Then, an identification and/or verification decision is made based on the processed audio signal and the processed video signal. Various decision making embodiments may be employed including, but not limited to, a score combination approach, a feature combination approach, and a re-scoring approach. In another aspect of the invention, a method of verifying a speech utterance comprises processing a video signal associated with a video source and processing an audio signal associated with the video signal. Then, the processed audio signal is compared with the processed video signal to determine a level of correlation between the signals. This is referred to as unsupervised utterance verification.

Abstract: A coding system includes methods and apparatus for producing a (0,6) run length limited rate 16B/18B code. The code produced is dc balanced and capable of operating near the theoretical performance limits for a 16B/18B code. This means the code is near optimum for run length and digital sum variation for a 16B/18B code. In one aspect of the invention, each 16-bit input data stream or block is broken into a 9-bit and a 7-bit sub-block and encoded separately while maintaining both dc balance and run length constraints across all block and sub-block boundaries. The present invention also provides a plurality of special purpose control characters such as commas, delimiters, idle characters, etc., by using the extra bits in the coded blocks whereby the special characters may be readily distinguished from data, while at the same time maintaining the dc balance and run length limitations in such characters. The 16B/18B transmission coding system of the invention also provides error correction techniques.

Abstract: Disclosed is a hardware design development tool, where in a first step the data flow (30) of the desired hardware design is specified (10, 40) and structured into functions. Then the required control logic (31, 32) is introduced in those functions in order to get a description of the functional behavior of the underlying hardware. Various interconnections or relationships are provided between data flow and control logic, for instance via calls (33) between them. According to the proposed methodological steps, the design is specified (10, 40) by functions depending on variables, wherein the functions contain data flow and control flow information. The functional description is parsed (43) in order to distinguish data flow and control flow information. In particular, at least one local table (45) each entry of which containing the control flow information, and a global table (46) each entry of which containing the data flow information and references to the local table(s), are provided.

Abstract: Fast and detailed match techniques for speaker recognition are combined into a hybrid system in which speakers are associated in groups when potential confusion is detected between a speaker being enrolled and a previously enrolled speaker. Thus the detailed match techniques are invoked only at the potential onset of saturation of the fast match technique while the detailed match is facilitated by limitation of comparisons to the group and the development of speaker-dependent models which principally function to distinguish between members of a group rather than to more fully characterize each speaker. Thus storage and computational requirements are limited and fast and accurate speaker recognition can be extended over populations of speakers which would degrade or saturate fast match systems and degrade performance of detailed match systems.

Abstract: A new clock distribution network design for VLSI circuits which effectively reduces skew without the area and power penalty associated with prior clock designs. Two wires emanating from the clock in opposite directions or, alternatively, two wires connected in series and running parallel, are used to route clock signals from the clock source to the next routing segment. The next routing segment routes clock signals to the tapping point near the circuit component by two emanated wires from the previous routing segment. Clock signals from the routing segments are fed through two-input NOR gates (alternatively, two-input NAND gates) to the clock pins. The clock signal arrival time is roughly equal to the simultaneous switching gate delay plus the average arrival times from the two paths, which turns out approximately the same across different tapping points, thus minimizing clock skews. Narrow wires may be used for routing, resulting in moderate power consumption.