Patents Represented by Attorney Peter M. Kamarchik
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Patent number: 8154900Abstract: Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.Type: GrantFiled: September 29, 2009Date of Patent: April 10, 2012Assignee: QUALCOMM IncorporatedInventors: Chiaming Chai, Jeffrey Herbert Fischer, Michael Thai Thanh Phan
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Patent number: 8151266Abstract: A fast sub-process is provided in an operating system for a digital signal processor (DSP). The fast sub-process executes a sub-process without a kernel first determining whether the sub-process resides in an internal memory, as long as certain conditions have been satisfied. One of the conditions is that a programmer determines that the sub-process has been previously loaded into internal memory and executed. Another condition is that the programmer has ensured that a process calling the sub-process has not called any other sub-process between the last execution and the current execution request. Yet another condition is that the programmer ensures that the system has not called another overlapping sub-process between the last execution and the current execution request.Type: GrantFiled: March 31, 2008Date of Patent: April 3, 2012Assignee: QUALCOMM IncorporatedInventors: Satya Jayaraman, Ashish Bajaj, Sachin Chaturvedi
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Patent number: 8145874Abstract: In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage.Type: GrantFiled: February 26, 2008Date of Patent: March 27, 2012Assignee: QUALCOMM IncorporatedInventors: Suresh Venkumahanti, Lucian Codrescu, Lin Wang
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Patent number: 8145883Abstract: A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set that is different from the first instruction set. The preloaded instructions are pre-decoded according to the second instruction set in response to an instruction set preload indicator (ISPI).Type: GrantFiled: March 12, 2010Date of Patent: March 27, 2012Assignee: QUALCOMM IncorporationInventors: Thomas Andrew Sartorius, Brian Michael Stempel, Rodney Wayne Smith
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Patent number: 8140823Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.Type: GrantFiled: December 3, 2007Date of Patent: March 20, 2012Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich James Plondke, Suresh Venkumahanti
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Patent number: 8127117Abstract: A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within a processing unit. The instruction is then executed to combine corresponding half word units from the source register units and to input the half word units into respective portions of a resulting destination register unit. During the execution of the instruction, the predetermined source register units are identified and corresponding most significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective most significant portion of a resulting destination register unit.Type: GrantFiled: May 10, 2006Date of Patent: February 28, 2012Assignee: QUALCOMM IncorporatedInventors: Mao Zeng, Lucian Codrescu
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Patent number: 8127114Abstract: A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to the execution stage within the processor. Partially or wholly executing the instruction prior to the execution stage in the pipeline speeds up the execution of the instruction and allows the processor to more effectively utilize its resources, thus increasing the processor's efficiency.Type: GrantFiled: March 28, 2007Date of Patent: February 28, 2012Assignee: QUALCOMM IncorporatedInventors: Kiran Ravi Seth, James Norris Dieffenderfer, Michael Scott McIlvaine, Nathan Samuel Nunamaker
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Patent number: 8122231Abstract: Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a software instruction of the program sets a mode of operation requiring a subset of the parallel processing capacity. At least one parallel processing element, that is not needed, can be shut down to conserve power. At a later time, when the added capacity is needed, execution of another software instruction sets the mode of operation to that of the wider data path, typically the full width, and the mode change reactivates the previously shut-down processing element.Type: GrantFiled: February 17, 2010Date of Patent: February 21, 2012Assignee: QUALCOMM IncorporatedInventor: Kenneth Alan Dockser
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Patent number: 8117420Abstract: A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.Type: GrantFiled: August 7, 2008Date of Patent: February 14, 2012Assignee: QUALCOMM IncorporatedInventors: Jian Shen, Robert Allan Lester
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Patent number: 8107492Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.Type: GrantFiled: August 31, 2006Date of Patent: January 31, 2012Assignee: QUALCOMM IncorporatedInventors: Richard Gerard Hofmann, Terence J. Lohman
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Patent number: 8099448Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.Type: GrantFiled: November 2, 2005Date of Patent: January 17, 2012Assignee: QUALCOMM IncorporatedInventors: Muhammad Ahmed, Ajay Anant Ingle, Sujat Jamil
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Patent number: 8082428Abstract: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.Type: GrantFiled: September 29, 2009Date of Patent: December 20, 2011Assignee: QUALCOMM IncorporatedInventors: Rodney Wayne Smith, Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius
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Patent number: 8082287Abstract: A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In one embodiment, parameters derived from the operands are altered such that when the multiply operation is performed on the altered parameters, the multiplier produces the saturated result. This may comprise altering a Booth recoded bit group to select a negative zero instead of a zero as a partial product, and suppressing the addition of the value one to the partial products (thus effectively subtracting the value one). In another embodiment, when the operands that will cause an overflow are detected, the output of the multiplier is forced to a predetermined saturation value.Type: GrantFiled: January 20, 2006Date of Patent: December 20, 2011Assignee: QUALCOMM IncorporatedInventors: Kenneth Alan Dockser, Bonnie Collett Sexton
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Patent number: 8078803Abstract: Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.Type: GrantFiled: January 31, 2007Date of Patent: December 13, 2011Assignee: QUALCOMM IncorporatedInventors: Thomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius
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Patent number: 8060701Abstract: When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.Type: GrantFiled: December 8, 2006Date of Patent: November 15, 2011Assignee: QUALCOMM IncorporatedInventors: Michael William Morrow, James Norris Dieffenderfer
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Patent number: 8008961Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).Type: GrantFiled: December 14, 2009Date of Patent: August 30, 2011Assignee: QUALCOMM IncorporatedInventors: Manish Garg, Chiaming Chai, Jeffrey Todd Bridges
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Patent number: 7996695Abstract: A circuit for reducing sleep state current leakage is described. The circuit includes a hardware unit selected from at least one of a latch, a flip-flop, a comparator, a multiplexer, or an adder. The hardware unit includes a first node. The hardware unit further includes a sleep enabled combinational logic coupled to the first node, wherein a value of the first node is preserved during a sleep state.Type: GrantFiled: February 15, 2008Date of Patent: August 9, 2011Assignee: QUALCOMM IncorporatedInventors: Martin Saint-Laurent, Jentsung Lin
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Patent number: 7996616Abstract: Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.Type: GrantFiled: January 31, 2007Date of Patent: August 9, 2011Assignee: QUALCOMM IncorporatedInventors: Thomas Philip Speier, James Norris Dieffenderfer, Thomas Andrew Sartorius
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Patent number: 7992062Abstract: A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.Type: GrantFiled: June 22, 2006Date of Patent: August 2, 2011Assignee: QUALCOMM IncorporatedInventors: Martin Saint-Laurent, Paul Bassett, Prayag Patel
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Patent number: 7986165Abstract: An apparatus is disclosed. In a particular embodiment, the apparatus includes a a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.Type: GrantFiled: February 8, 2010Date of Patent: July 26, 2011Assignee: QUALCOMM IncorporatedInventors: Jentsung Lin, Paul Douglas Bassett