Abstract: A system for suppressing transient noise in switched-mode amplifier systems is disclosed. An amplifier, for amplifying a signal from a digital signal source includes a first complementary metal oxide semiconductor field effect transistor (MOSFET) pair. A common node of the pair is serially coupled to an output node of the amplifier by a resistor. The first MOSFET pair is configured to drive a ramp on the output node of the amplifier.

Abstract: A virtual memory manager for a multi-media engine allows individual media units to operate in their own virtual space in much the same way as a software program operating in virtual mode. The virtual memory controller performs address translation or mapping to the correct physical memory location (in local memory or system memory) and will also convert the data stream to or from a compressed format. In addition, the virtual memory controller provides a unified TLB (translation lookaside buffer) available to all media units. The TLB has four types of pointer entries which are controlled by two bits. The first bit controls whether the TLB entry is a direct map or a pointer to another translation table. the second bit controls whether the TLB entry is stored in a compressed format. The overall concept may allow dynamic load balancing between local media memory and system memory.

Abstract: Audio data processing circuitry 300 includes a plurality of analog inputs 101 for receiving analog audio data and a digital input 105 for receiving digital audio data. A analog mixer 312 mixes analog data received at said plurality of analog inputs 101 to generate a mixed analog audio stream. An analog-to-digital converter 313 converts the mixed analog audio stream to a digital audio stream and a digital mixer 315 mixes digital data received at the digital input 105 with the digital audio stream from the analog mixer 312 to generate a mixed digital audio stream.

Abstract: Real-time synchronized voice communications during a multi-player game is disclosed. A server is connected to client computers, players. Players can speak into a microphone and have their voice transmitted to all players or a select few. Digitized voice communications are transmitted along with other game data. Player speech and game data is synchronized and reproduced in the same order it was captured.

Abstract: DOS application programs are accommodated when using a controllerless modem by providing a virtual device driver. The virtual device driver emulates UART to UART communications and handles interrupts by the DOS applications and by a hardware port managed by the controllerless modem. In one implementation, the virtual device driver shares a communications interface in common with 32-bit applications. In a communication system environment, DOS applications can participate in modem to modem communications with remote DTEs and with other devices using the services of the virtual device driver.

Abstract: The present invention allows a single display controller design to be used in multiple markets by providing an additional stand-alone circuit which converts conventional analog CRT display signals to digital flat panel display or other digital display signals. A single VGA CRT controller may be implemented in both desktop and portable (e.g., laptop) markets thereby reducing the cost of the display controller through the economies of scale. For a laptop or other digital display markets, the apparatus of the present invention may be applied to a conventional analog CRT controller to convert analog CRT signals to digital laptop signals to generate a display on a flat panel display or other digital device. In addition, the apparatus of the present invention may be incorporated into a stand-alone flat panel display intended for use as a replacement for conventional CRT monitors. The apparatus of the present invention accepts a conventional analog CRT input and outputs digital flat panel display signals.

Abstract: A video controller for controlling at least two video displays incorporates a video memory for storing first and second video frames of interleaved pixel data. A video memory controller connected to the video memory sequentially reads data for a first pixel from the first video frame and data for a second pixel from the second video frame. Each pixel data is in turn transferred to a look-up table connected to the video memory controller which converts the first and second pixel data to first and second display data. A selector coupled to the look-up table alternately routes the first display data to one video display and routes the second display data to the other video display.

Abstract: An image displayed on a digital display such as a flat panel display is rotated while the same image is displayed on a cathode ray tube display in unrotated form. When image rotation is selected, the read address sequence into a frame buffer may be reversed and the bit read sequence may be reversed. Thus a frame of panel pixel data stored within the frame buffer of an external video memory may be scanned onto a flat panel to display a rotated image.

Abstract: A method of automatically detecting a data format type of a stream of data. A determination is made as to whether a current word and a previously received words comprise a set of identifiers associated with a selected type of data. When a preselected number of detections of the set of identifiers has been reached within a predefined time period, the input stream is declared to be the selected type of data. Simultaneously, when the selected type of data is not detected, other data types are sequentially selected for similar checking. This successive selection of different data types allows the method to classify the input data into one out of multiple data types.

Abstract: A method and apparatus are used to continuously convert a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information for controlling the ADC components to produce a digital sample of the analog signal on the specified physical channel. At least one looping bit and at least one depth bit are also stored in a register on the serial port. The depth bit indicates a number of logical channels in one data scan. At least that number of logical channels are stored in the register. In response to a command bit indicating conversion mode, a quantity of data scans is output on a serial output pin of the serial port interface.

Abstract: A graphics system including a selectable mode smoothing filter for improved texture mapping. An x, y pixel coordinate is mapped into a u, v texture map. The mapped u, v coordinate includes integer and fractional portions. Depending on the location of the coordinate relative to the four nearest texels, which are represented as integers, one of several texture mapping schemes are used to either select or calculate the texel value to be used to render the pixel at the x, y screen location. The three texture mapping schemes include point sampling in which the nearest texel from the texture map is selected, two-texel averaging in which the closest two texels are combined in a weighted average, and four-texel averaging in which the closest four texels are combined in a weighted average. Scale factors in the range of 0 to 1 are computed for averaging texel values together.

Abstract: An extended V.8bis command sequence enables a DTE to configure a DCE for alternative configurations and for independent V.8bis protocol negotiations. The DCE can be configured by sending it an AT command sequence as part of an initialization string. In this way, legacy applications can use the full capabilities of modems without rewriting the legacy application code.

Abstract: A high performance test signal generator uses a digital to analog converter which converts an N-bit digital signal, such as provided by a computer waveform generator or by a CDROM into an M-bit upsampled digital signal. The M-bit digital signal is applied to an M-bit digital to analog converter to produce an analog output signal. The analog output signal is sampled and fed back across, the discrete time/continuous time interface to the input of the conversion circuit. The test signal generator has very low power consumption yet meets very strict noise and linearity requirements. The test signal generator can be used for testing seismic sensors such as geophones or hydrophones.

Abstract: A graphics system includes a graphics controller for rendering polygons with texture using an improved MIP mapping technique in which texels from multiple MIP maps are blended together. The graphics controller includes a polygon engine for rendering the pixels in a polygon and at texture map engine for selecting texture elements ("texels") from an appropriate texture map to be applied to the pixels rendered by the polygon engine. The texture map engine generates texel coordinate values from pixel coordinate values provided by the polygon engine. Texel values are selected from a set of texture maps each map varying from the others by the level of detail of the texture in each map. The graphics controller computes a scale factor for each texel value according an are a bounded by adjacent texel coordinates generated by the texture map engine. The scale factor is then used to compute a weighted average of texels form more than one MIP maps.

Abstract: A technique for reducing jitter on a data channel utilized for transfer of data between components disposed on the channel. Instead of coupling a ground of the channel directly to a ground network of a chip containing the data transferring device, an impedance between the channel ground and a substrate is utilized to minimize the jitter.

Abstract: A V.34 compliant modem uses a noise whitening filter to compensate for noise enhancement in an equalizer. The noise whitening filter uses a 3 tap FIR the response of which is determined by 3 coefficients. The coefficients are derived using a newly developed extension of the Levinson-Durbin algorithm to complex numbers. The coefficients thus derived are used to control the precoder as well as the noise whitening filter. The coefficients are also used to control precoding reconstruction after the decoder.

Abstract: A technique for providing a start-up circuit for a bandgap reference. An amplifier configured in a differential arrangement as the bandgap reference. A start-up circuitry ensures that a second input node is maintained at a lower voltage than a first input node of the amplifier at start-up, when the output node corresponding to the second input side of the amplifier is also pulled low.

Abstract: A graphics system including a selectable mode filter for improved texture mapping. An x, y pixel coordinate is mapped into a u, v texture map. The mapped u, v coordinate includes integer and fractional portions. Depending on the location of the coordinate relative to the four nearest texels, which are represented as integers, one of several texture mapping schemes are used to either select or calculate the texel value to be used to render the pixel at the x, y screen location. The three texture mapping schemes include point sampling in which the nearest texel from the texture map is selected, two-texel averaging in which the closest two texels are combined in a weighted average, and four-texel averaging in which the closest four texels are combined in a weighted average. By providing a selectable filter than can perform point sampling or two or four-texel averaging, the speed benefit of point sampling can be approached as well as the superior quality of two and four-texel averaging.

Abstract: A multi-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.

Abstract: A digital to analog converter utilizes two discrete time processing stages, such as switched capacitor integrator circuits, operating at different sampling rates when converting the digital input signal to an analog signal. Use of two different sampling rates relaxes the requirements on antialias filters used in the continuous time processing.