Abstract: The specification describes an improved optical fiber ribbon cable. The cable design addresses the problem of wrinkles in the cable coating that occur on the interior bend radius on moderate bending of the cable. The wrinkles are much smaller than the bend radius, and are, relatively speaking, microbends. These may cause microbending losses in the fibers even where the bend radius is relatively large. The cable design of the invention has a combination of three important features. The cable cross section is round. The encasement for the optical fiber stack is relatively hard, and is deliberately made to adhere to the optical fiber stack. Consequently the encasement medium functions as an effective stress translating medium that deliberately translates stresses on the cable to the optical fibers. The optical fibers function as compressive strength members to retard longitudinal strain on the cables, and thereby reduce wrinkling of the encasement.

Abstract: The specification describes interconnection techniques for interconnecting large arrays of micromechanical devices on a silicon platform. The problem of interconnection congestion is overcome by routing the interconnections through the substrate. The through interconnections are made by etching vias through the substrate by RIE, oxidizing the via sidewalls, and filling the vias with polysilicon.

Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.

Abstract: The specification describes integrated circuit air isolated crossover interconnections designed for flip chip multi-chip module interconnection technology. The crossovers are made using a crossover interconnection substrate separate from the interconnection substrate of the integrated circuit. In one embodiment the integrated circuit is flip chip bonded to a multi-chip or multi-component interconnection substrate, and the crossover interconnections are made through solder bumps or balls soldered to a conductive layer on the crossover interconnection substrate. In another embodiment the crossover is made via a crossover substrate flip chip bonded to an integrated circuit mounted on a multi-chip or multi-component interconnection substrate.

Abstract: The specification describes electrical testing strategies for multi-chip modules (MCMs). The MCMs are fabricated on double sided substrates, which are then solder bump bonded to a motherboard to form a BGA package. Untested chips are attached permanently to one side of the substrate to form a partially completed MCM package (PCMP), and the PCMPs are tested. PCMPs that pass are then completed by assembling known good die on the other side of the substrate.

Abstract: The specification describes a multi-chip IC package in which IC chips are flip-chip bonded to both sides of a flexible substrate. The upper (or lower) surface of the flexible substrate is bonded to a rigid support substrate with openings in the support substrate to accommodate the IC chips bonded to the upper (or lower) surface of the flexible substrate. In a preferred embodiment a plurality of IC memory chips are mounted on one side of the flexible substrate and one or more logic chips to the other. A very thin flexible substrate is used to optimize the length of through hole interconnections between the memory and logic devices. If logic chips are flip-chip mounted in the cavity formed by the openings, a heat sink plate can be used to both cap the cavity and make effective thermal contact the backside of the logic chips.

Abstract: The invention relates to plastic optical fiber (POF) processes and systems and involves improved non-polishing termination techniques. The techniques provide good physical and optical characteristics, i.e., smoothness, at the termination point, thereby providing lower losses than conventionally obtained. According to one embodiment, POF is cut while the fiber is under compression. According to another embodiment, the POF is notched and then pulled at a relatively high strain rate to induce fracture. The rate is such that the strain remains in the elastic region, i.e., the fiber exhibits brittle, as opposed to ductile, behavior during the strain. The brittle behavior provides a smooth termination surface, as opposed to a plastically-deformed surface.

Abstract: The specification describes a water blocking tape for an optical fiber cable wherein the optical fibers in the cable are wrapped with a synthetic fibrous non-woven tape coated with a superabsorbent polymer powder coating. The particles in the powder are ultra-fine, i.e. have less than 7% weight fraction over 300 microns in diameter. Controlling the particle size within this range is found to reduce microbending losses in the optical fiber.

Abstract: A photorecording medium contains a polymeric matrix, typically cross-linked to provide a desired level of physical stability, and a photoimageable system containing a photoactive monomer. Unlike previous polymer media, which tend to contain a substantially homogeneous dispersion of photoimageable system and matrix polymer, the matrix and photoimageable system of the invention are phase separated, yet still exhibit low light scattering such that useful holographic properties are possible.

Abstract: The specification describes a process for forming a barrier layer on copper metallization in semiconductor integrated circuits. The barrier layer is effective for both wire bond and solder bump interconnections. The barrier layer is Ti/Ni formed on the copper. Aluminum bond pads are formed on the barrier layer for wire bond interconnections and copper bond pads are formed on the barrier layer for solder bump interconnections.

Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on IC chips with Al bonding sites. The UBM of the invention comprises a copper layer applied directly to the aluminum bonding sites. Reliable bonds are obtained if the Al surface is a nascent surface. Such a surface can be provided by back sputtering an aluminum bonding site, or by a freshly sputtered aluminum layer. The copper layer is deposited on the nascent aluminum surface in e.g. a cluster tool without breaking vacuum. The UBM can be patterned using subtractive techniques.

Abstract: The memory element of the present invention utilizes a substrate, a first conductive connection, a second conductive connection, and an ionic layer. The substrate includes a source region, a drain region, and a channel region, which is disposed between the source region and the drain region. The ionic layer includes ions and is coupled to the substrate. The first connection is coupled to the source region, and the second connection is coupled to the drain region. An electrical field is applied through said ionic layer such that the ions in the ionic layer move. When the memory element is to exhibit a logical high state, the polarity of the electrical field causes the ions to move toward the channel region. This pulls the electrons in the source and drain regions into the channel region making the channel region conductive. When the memory element is to exhibit a logical low state, the polarity of the electrical field causes the ions to move away from the channel region.

Abstract: The specification describes silicon MOS devices with gate dielectrics having the composition Ta1−xAlxOy, where x is 0.03-0.7 and y is 1.5-3, Ta1−xSixOy, where x is 0.05-0.15, and y is 1.5-3, and Ta1−x−zAlxSizOy, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.

Abstract: An interferometric system includes first, second and third optical fibers with first and second couplers. The first coupler is configured to receive radiation through the first fiber, provide a first radiation portion through the second fiber and provide a second radiation portion through the third fiber to the second coupler. The system also includes fourth and fifth optical fibers each configured to receive radiation from the second coupler and transmit radiation for receipt by the other.

Abstract: The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate thereby increasing the current handling capabilities of the ESD. The trench also provides a convenient buried contact to the RF ground.

Abstract: The specification describes a connector for joining optical elements, especially optical fibers. The connector is a sleeve made of a Simple Shaped Memory Polymer (SSMP) into which the optical fiber is inserted and the sleeve heated to collapse the sleeve around the optical fiber. The SSMP materials are not crosslinked and can be manufactured by a variety of techniques including extrusion. Various methods for forming the bore of the connector and expanding the size of the bore from the memory state to the metastable state are described.

Abstract: The use of silica powders having large particle sizes in making sol-gel silica bodies has been found to have important advantages. Among these are higher gel strength, higher silica loading, more rapid aging and drying of the gel, a reduction in the amount of organic additives leading to reduced process time required for organic burn-off, and easier removal of contaminant particles due to their larger size. It was also discovered that spherical particle morphology contributes to the improved properties.

Abstract: The specification describes ceram-glass compositions useful for electro-optic devices. The compositions have active ferroelectric ingredients in a tellurium oxide host. Proper processing of the ceram-glass produces highly transparent material with desirable ferroelectric properties. The ceram-glass materials can be used for electro-optic devices in both bulk and thin film applications.

Abstract: The specification describes a method for monitoring a characteristic of a mixture of particles suspended in a liquid medium by generating a first interference signal by combining first and second radiation beams after the first beam traverses a reference path and the second beam traverses a path extending into the mixture, allowing the particles in the mixture to partially settle, then generating a second interference signal by the same technique as used for the first. The second interference signal is then compared to the first interference signal to determine a change in, e.g., the particle density.

Abstract: The specification describes a dual level gate for reducing hot carrier effects in MOS transistors. The dual level gate is formed by undercutting the edges of the gate using a wet etch, and growing oxide in the undercut to a thickness exceeding the gate oxide thickness, thereby lifting the edge of the gate and reducing the electric field concentration at the drain edge of the gate.