Abstract: This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more than 15 consecutive logic zero bit positions. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing. Intermediate storage octets are utilized to contain addresses of an all zero octet. This scheme provides for minimal buffering at the encoding system, which facilitates error detection and correction by the decoding system.

Abstract: This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more then 15 consecutive logic zero bit positions. In addition, a proper AMI signal should contain a logic 1 density of an average of one logic 1 per 8-bits of information over every consecutive 3 octet group. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing.

Abstract: This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more than 15 consecutive logic zero bit positions. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing. This scheme provides for minimal buffering at the encoding system, which facilitates error detection and correction by the decoding system.

Abstract: The present method is an encoding scheme for suppressing excessive amount of zeroes transmitted via a T1 line facility. Clear channel transmission capability is provided by this scheme for 32 kb/s or 64 kb/s transmission channels. This scheme provides the proper zero bit suppression for alternating mark inversion signaling (AMI). A proper AMI signal contains no more than 15 consecutive zero bit positions. In addition to meeting the AMI signaling standards, this scheme does not induce any violations of VMR (violation monitor and removal) equipment. Thus, this scheme is transparent to existing line equipment and error monitoring equipment. This scheme provides both a necessary and sufficient method for achieving the AMI signaling requirements during clear channel signaling.

Abstract: Telecommunication switching systems are typically connected by high-speed digital data spans. These spans may commonly be T1 or T2 carriers using DS1 or DS2 data formats, respectively. These systems may contain duplex digital span control units. The present synchronization arrangement is an additional duplex control circuit. This synchronization arrangement includes a time multiplexed state machine for each copy of the digital span control unit. The state machine monitors data ready signals from its own copy as well as from the other copy of the digital span control unit. Other signals indicate whether the circuit is operating in a simplex or duplex mode and which circuit is the active and which is the standby copy. This circuitry detects whether the data ready signals for each copy are identically synchronized. If these data ready signals are not identically synchronized, then one copy of the circuitry waits a predetermined scan cycle time for the other copy of the circuit to catch up.

Abstract: Telecommunication switching systems are typically connected by high-speed digital data spans. These spans may commonly be T1 or T2 carriers using DS1 or DS2 data formats, respectively. These systems may contain duplex digital span control units. Synchronization circuitry includes a time multiplexed state machine for each copy of the digital span control unit. The state machine monitors framing alarm signals from its own copy as well as from the other copy of the digital span control unit. This circuitry detects whether the framing alarm signals for each copy are identically synchronized. If these framing alarm signals are not identically synchronized, then one copy of the circuitry executes a hold (wait) operation for the other copy of the circuit to perform its reframing operation. For non-error conditions, the wait places the two copies back in synchronization.

Abstract: This circuit provides for the connection of simplex I/O terminals to duplex processor copies. Each processor copy's configuration provides for a terminal control circuit. These copies of the terminal control circuit are cross connected in order to provide access from each processor to each I/O terminal. Normal operation consists of a particular I/O terminal being operated by one processor copy. If the processor copy corresponding to a particular terminal is faulty or removed from service, that terminal is then automatically cross-connected to the active processor copy and receives output from that processor copy. If one processor copy is out of service, both I/O terminals receive output from the active processor copy. If the I/O terminal which is normally connected to the active processor copy becomes out of service and the other processor copy is out of service, the I/O terminal which is normally connected to the other processor copy will be reconfigured to be connected to the active processor.

Abstract: An arrangement for transmitting data messages between a CENTREX equipped central office exchange and a remotely located attendant console. The arrangement includes an operating unit residing in an interface circuit connected between the CENTREX and the attendant console. The operating unit includes sequential memory connected to the CENTREX and to a controller arranged to receive and store data message from the CENTREX. The CENTREX sends a data available signal to the controller signaling that a data message is available for transfer from the sequential memory. In response, the controller sends the CENTREX a sequential memory read control signal signaling that the controller is reading the sequential memory. State machine called by the controller transfers a first byte of the data message from the sequential memory to temporary memory.

Abstract: This invention is a circuit for generating a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position.

Abstract: Simplified CCIS (Common Channel Interoffice Signalling) data transfer circuitry is shown for transmitting data between a CCIS central processing unit of a central switching office and a number of terminal equipment controllers, each having a local CPU. The terminal equipment controller operates such equipment as modems of various speed, digital trunks or T1 spans. This design minimizes the amount of circuitry required to transmit CCIS data between central processing units, thereby permitting a more reliable design. This circuit provides a minimal amount of logic required for interprocessor communication. In addition, this circuit minimizes the amount of real time required by each CPU to perform the CCIS data transfer.

Abstract: An arrangement for splicing and aligning two fiber optic cables is disclosed comprising a fixed connector stage and a movable connector stage. The fixed connector stage includes a fiber optic connector having a first fiber optic cable mounted therein. The first fiber optic cable has one of its ends connected to a source of light energy. The movable connector stage also includes a fiber optic connector having a second fiber optic cable housed therein. The two connector stages are located adjacent to the other with the two optical fibers coarsely aligned alog a horizontal axis. An alignment fixture is then mounted to the movable connector stage and an end of the second fiber optic cable connected to a photo-detector device. The light detector is electrically connected to a control device with the control device in turn electrically connected to the alignment fixture.

Abstract: An arrangement for tranmitting data messages between a remotely located attendant console and a CENTREX equipped central office exchange. The arrangement includes an operating unit residing in an interface circuit connected between the attendant console and the central office exchange. The operating unit of the present invention includes receiving circuitry connected to the attendant console and to a controller. The receiving circuitry is arranged to receive a data message from the attendant console and set a receive signal. A state machine called by the controller transfers the first byte of the data message to a temporary memory and resets the receive signal. The state machine accepts all additional characters from the receiving circuitry storing received characters in the memory until a character sequence is received indicating the end of the data message. When a complete data message is received an analysis is called by the controller which analyzes the received data message.

Abstract: An arrangement for initializing an interface circuit connected between a CENTREX equipped central office exchange and a remotely located attendant console. The arrangement includes an operating unit residing in the interface circuit. The operating unit includes a controller connected to memory and to the CENTREX. The controller receives an initialization signal from the CENTREX and returns an initialization in progress signal. Memory verification called next by the controller ascertains if all locations in the memory are operable. The controller sends an error signal to the CENTREX in the event the memory verifications detects an error. Next, interface initialization called by the controller resets and clears a sequential memory and resets and clears a send/receive circuit connected to the controller and the attendant console. Transmission verification called next by the controller checks if the transmit and receive loop between the attendant console and the interface circuit is operable.

Abstract: An interface circuit for transmitting data messages between a remotely located attendant console and a CENTREX equipped central office exchange. The interface circuit includes control and sense decoders connected to control and sense fields. Receiving circuit connected to the attendant console receive data messages transmitted from the attendant console. A controller connected to the receiving circuit process the received data messages, storing the data messages in a temporary memory. Sequential memory connected to the temporary memory receive and store in sequential order the data messages after they are processed. The sequential memory further includes memory enabling circuit connected to the control and sense decoder.

Abstract: This circuitry expands the memory addressing arrange of a microprocessor beyond its directly addressable memory capacity. This circuit uses the status outputs of the microprocessor to segregate memory accesses for program code instructions from accesses for other data. This segregation scheme assigns different memory banks to program code instructions and to data. Memory reads and writes for scratch pad data are performed from one bank of memory. Memory reads for program code instructions are performed from a separate memory bank. This memory bank technique can double the size of a microprocessor's directly addressable memory without changing the microprocessor's architecture. This circuitry is suitable for implementation with CMOS gate array technology.