Abstract: A fiber image guide is used for establishing bit-parallel computer data communications. A fiber image guide is located between an input laser array driven by a first electrical circuit or computer chip and a receive detector array coupled to a second electrical circuit or computer chip for transmitting bit-parallel data from the first electrical circuit or computer chip to the second electrical circuit or computer chip.

Abstract: Feature grouping of moving rigid bodies in an image is accomplished by processing a sequence of two-dimensional orthogonal projection of a three-dimensional scene containing a plurality of such independently-moving rigid bodies.

Abstract: A method of high level circuit design synthesis using transformations based upon the addition of deflection operations reduces the interconnects and register requirements as well as the area requirements of a circuit design while preserving throughput without increasing the number of execution units needed. The method may also be applied to reduce the partial scan overhead for generating testable datapaths. The overall result of the transformations is to improve resource utilization and/or testability of circuits so designed.

Abstract: A fuzzy syllogistic inference processing system for use with a chain of implications when links in the chain have various measures between 0 and 1 of confidence. Analog signals that are linearly related to the confidence measures are generated and compared. The chain of implications is given a confidence measure that is equal to that of the inference consequence of the last major premise in the chain provided that each major premise in the chain has a confidence measure that is larger than the confidence measure of the complement or negation of its antecedent in the chain.

Abstract: A mesh-connected tree (MCT) interconnect topology network which is a two-dimensional interconnect topology combining aspects of a conventional tree-network and a two-dimensional nearest-neighbor mesh network is implemented as a planar optical interconnect network.

Abstract: An asynchronous transfer mode (ATM) traffic control framework is based on an integrated usage parameter control (UPC) approach, which approach provides a unified and scalable solution to the issue of quality-of-services (QOS) levels over a range of anticipated services in ATM based networks. The approach is consistent with emerging ATM Forum and CCITT standards. Additionally, a UPC-based call and burst admission control providing the desired QOS over periods of network overload by call/burst admission control and traffic shaping of source stream preferably uses a dual leaky bucket.

Abstract: In partial scan testing of integrated circuits, for an arbitrary graph of an integrated circuit, a Boolean function is derived whose satisfying assignments directly correspond to feedback vertex sets of the graph. The Boolean function is then used for determining the minimum cost feedback vertex set. Boolean function representation using Binary Decision Diagrams (BDI)) in logic synthesis is used to solve the problem of representing the Boolean function efficiently, even for large graphs. The determined minimum cost feedback vertex set is used to select those memory elements in the integrated circuit comprising the scan chain.

Abstract: Non-scan design-for-testability methods for making register-transfer-level data path circuits testable include using EXU S-graph representation of the circuits. Loops in the EXU S-graph are made k-level controllable/observable to render the circuit testable without having to scan any flip-flops or break loops directly. Moreover, the resultant circuit is testable at-speed.

Abstract: A method for performing high level synthesis of integrated circuits simultaneously considers testability and resource utilization. The method considers the relationship between hardware sharing, loops in the synthesized data path, and partial scan testing overhead. Hardware sharing is used to minimize the quantity of scan registers required to synthesize data paths with a minimal quantity of loops. A random walk based algorithm is used to break all control data flow graph (CDFG) loops with a minimal quantity of scan registers. Subsequent scheduling and assignment avoids the formation of loops in the data path by reusing the scan registers, while ensuring high resource utilization of the components of hardware costs: execution units, registers and interconnects. The partial scan overhead incurred is less than that of conventional gate level design partial scan techniques.

Abstract: A method based on continuous optimization techniques for generating test vectors for use in testing VLSI circuits includes representing digital circuits as smooth functions. The test generation problem is formulated as the minimization of the objective function over a hypercube in Euclidean space. The dimension of the space is equal to the number of primary inputs of the circuit. The smooth function is optimized inside a convex polytope using a variant of gradient descent and line search strategies. The solution starts at the center of the hypercube and follows a trajectory to one of the corners of the hypercube that corresponds to a test vector. Once the test vector is determined by this method, electrical signals corresponding to the test vector are applied to the inputs of the VLSI circuits. The outputs of the VLSI circuit are monitored in order to locate defects in the circuit.

Abstract: In partial scan testing of a circuit the optimal quantity of scan flip-flops required to eliminate all feedback, except self-loops, in a circuit is determined. For determining a minimal feedback vertex set (MFVS) for the S-graph of a circuit to be tested, MFVS-preserving transformations, partitioned search strategy and integer linear program (ILP)-based lower bounding techniques are combined to obtain an exact algorithm for computing the MFVS. The result is used in the fabrication of the circuit with minimal overhead in terms of area and performance degradation as a result of providing the capability to perform partial scan testing of the fabricated circuit.

Abstract: High level synthesis of datapaths has traditionally concentrated on synthesizing a specific implementation for a given computational problem. Methods to compose a reconfigurable BISR (built-in-self-repair) implementation with a minimum amount of area overhead are disclosed. Previously the BISR scope has been restricted to the substitution of operation modules with only those of the same type. Novel resource allocation, assignment and scheduling and transformation methods, primarily for ASIC designs, are described. These methods are based on the exploration of the design solution space accomplished by use of high level synthesis processes to find designs where resources of several different types can be backed up with the same unit.

Abstract: A method of selecting circuit elements in a sequential circuit for partial scan testing relies upon analyzing and breaking reconvergence through the selected circuit element. Different types of reconvergences present in the circuit and their affect on the circuit testability are considered. Harmful reconvergence present in the circuit are broken by scanning a memory element present in the reconvergence path.

Abstract: A partial scan methodology selects scan flip flops (FFs) in the minimum feedback vertex set (MFVS) of the FF dependency graph so that all loops, except self-loops, are broken. The MFVS of the circuit, i.e. the minimum quantity of gates whose removal makes the circuit acyclic, is a lower bound and in many cases is significantly smaller than the MFVS of the dependency graph. Since only FFs arc considered for scan, FFs are repositioned so that, in a modified circuit, every circuit MFVS gate drives one FF that can be scanned. A method is disclosed by which resynthesis and retiming can always transform any circuit into an equivalent circuit whose FF dependency graph MFVS is equal to the MFVS of the original circuit. Therefore, the MFVS of a circuit is a lower bound on the quantity of scan FFs needed. The necessary and sufficient conditions under which legal retiming can produce the desired FF repositioning are identified.

Abstract: Methods of traffic smoothing for frames of different video sources where each video source transmits frames at fixed intervals and the network is free to decide the relative temporal spacing of video frames from different sources provide significant performance advantages. The time at which a given source begins to transmit its first frame is under the control of the network; however, thereafter, all frames from the source are transmitted at fixed intervals. Two heuristic and one optimization method control the temporal placement of the video frames from different sources in order to reduce the loss rate of the high priority cells and to minimize the smoothness index of the traffic.

Abstract: A number-theoretic based algorithm provides for secure electronic voting. A voter may cast a votes among n centers in a manner which prevents fraud and authenticates the votes. Preprocessing allows for nearly all of the communication and computation to be performed before any voting takes place. Each center can verify that each vote has been properly counted. The algorithm is based on families of homomorphic encryptions which have a partial compatibility property. The invention can be realized by current-generation PCs with access to an electronic bulletin board.

Abstract: A method of asynchronous circuit synthesis of initializable circuits from signal transition graphs (STG) that are either functionally initializable or functionally uninitializable is described. For functionally initializable cases, an initializable implementation can be achieved by proper assignment of don't care values. If the STG is not functionally initializable, the sources of uninitializability in the STG are identified and the STG is transformed into a functionally initializable specification by exploiting concurrency. Initializability is achieved at the expense of minimal removal of concurrency. Moreover, the transformation does not violate liveness and unique state coding properties of the STG. When the STG is functionally initializable or after an uninitializable STG is transformed to become functionally initializable the result is an initializable circuit design.

Abstract: A metallurgical joint structure between two workpieces to be joined by soldering or brazing includes a stress release layer of a low yield point metal, preferably silver, gold, copper, palladium or platinum. The joint structure also includes a juxtaposed barrier layer to prevent the diffusion of a solder element, such as tin, to the stress release layer. Preferred barrier layers are chromium, titanium-tungsten and tantalum. Preferably, the joint includes one or more stress relief layer and associated barrier layer combinations in the joint structure for improved joint reliability.

Abstract: A k-fault tolerant AND gate circuit comprises k+1 levels and the input level comprises k+1 AND gates. Embodiments provide intermediate levels arranged for providing a two-fault tolerant AND gate circuit and a four-fault tolerant AND gate circuit, respectively.

Abstract: A control method and architecture is described for an ATM network carrying connectionless data traffic. The method is capable of integrating connection-oriented as well as connectionless traffic. The method takes advantage of the quasi-deterministic nature of the traffic emanating from a source that is being shaped by the leaky bucket shaping algorithm. Alternative methods are provided if such a shaping algorithm is not provided by the CPE which methods still guarantee performance that equals or exceeds shared media networks such as FDDI. Hardware and software embodiments of the methods are disclosed. The invention is particularly applicable to LANs and hubs.