Abstract: The invention relates to a method and an apparatus for distribution of bandwidth in a switch or router. More particularly, the invention relates to a scheduler and an associated algorithm for distributing bandwidth over data traffic directed to output ports and received in various traffic classes and flows. The switch has a switching fabric. Preferably, the bandwidth scheduler is located before output queues, and the method includes: receiving a stream of data from the switching fabric; subjecting the stream to a decision making algorithm in the bandwidth scheduler resulting in that the stream is forwarded or interrupted (accepted or rejected). Preferably, the stream of data includes identifiable data packets and the decision making algorithm in the bandwidth scheduler results in the data packet being accepted or rejected. The bandwidth scheduler may be located before the output queues leading to early discarding of packets and efficient use of output buffer memory.

Abstract: A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.

Abstract: A device for data stream analyzing that is able to recognize different data streams and then start processors or functionalities to store or check data in a data stream. The device includes a processor means and a program memory, making it possible to parse a data stream in a way that is controlled by an interchangeable program. There will be no need for changing the hardware. This could save time and money for companies responsible for providing, maintaining and updating network switches. The device also includes a multiplexable data stream delayline for receiving the data streams, and multiplexing means for connecting different parts of the data stream to the processor.

Abstract: The invention presented herein relates to methods and systems for providing life management and enhancement applications and services to customers via an electronic medium such as the Internet. In addition, the present invention is directed to business-to-business and business-to-customer applications that provide customer-centric and “reverse retailing” services to customers. The life management and enhancement applications and services are provided to customers through a central online location such as the Internet portal. A system and method according to one particular embodiment of the present invention describes an application for providing telematics services to the customer.

Abstract: A system for providing simultaneous, real-time trace and debug of a multiple processing core system on a chip (SoC) is described. Coupled to each processing core is a debug output bus. Each debug output bus passes a processing core's operation to trace capture nodes connected together in daisy-chains. Trace capture node daisy-chains terminate at the trace control module. The trace control module receives and filters processing core trace data and decides whether to store processing core trace data into trace memory. The trace control module also contains a shadow register for capturing the internal state of a traced processing core just prior its tracing. Stored trace data, along with the corresponding shadow register contents, are transferred out of the trace control module and off the SoC into a host agent and system running debugger hardware and software via a JTAG interface.

Abstract: An electro-statically actuated switch having a reduced gap distance between electrodes for reducing actuation voltage is provided. The invention provides more reliable electro-statically actuated switches. The invention provides a micro-electro-mechanical system (MEMS) that includes a recessed, movable electrode. The invention provides electro-statically actuated switches that reduce the likelihood of stiction and beam deformation and that allows lower actuation voltage for electrostatically actuated structures such as switches and mirrors. A method for fabricating such a design is provided that allows lower actuation voltage.

Abstract: The invention relates to a method for flow control in a switch and a switch controlled thereby. In order to ensure that no or few packets are dropped in a switch because of a congested internal memory, pause frames or stop command messages are sent to upstream senders. When to send pause frames are determined by monitoring the buffer contents of the switch and estimating the total expected contents of the links between the senders and the switch. The pause frames are sent to the most offending senders, i.e. the senders causing the largest queues in the switch.

Abstract: A garment facility produces custom-made garments according to the body contour and the fit preferences of a customer. Try-on garments for various styles of garments are presented to customers for selection. The tailor will retrieve the one or more base patterns associated with the try-on garment. The pieces of the base patterns are marked and modified according to both the body contour and the fit preferences of a customer and connected as sample garment for try-on. The marked pieces are recorded and sent to a cutting machine as digital data. Multiple try-on garments can be combined to form new sample garments. A favorite garment of the customer can be recorded as digital data to re-produce the custom-made garments.

Abstract: A data encoding scheme maps a set of data to a number of spectral components, each component having an amplitude, a phase and a unique frequency. From these mapped tones, an analog baseband signal can be formed, which, when implemented in a data transmission scheme, can realize much higher throughput per available bandwidth than conventional techniques such as those employing binary baseband signals. The encoding scheme can also be implemented in data compression schemes and can realize lossless compression ratios exponentially superior to conventional compression schemes.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: An interface is provided between a conventional telephone and a conventional computer configured for network voice applications including a sound card and modem. The interface allows for use of the telephone during network voice applications such as IP telephony and voice chat. When the telephone is not used, the interface allows for sound to be input and output via the computer sound card and conventional computer microphone and speakers. When the telephone is picked up off-hook, the interface senses the off-hook state, causes the computer sound card to be connected to the telephone instead of the conventional microphone and speakers, and allows for network voice applications to be conducted using the telephone.

Abstract: A wireless gateway architecture integrates support for a plurality of wireless standards and protocols. In accordance with the architecture of the invention, a wireless gateway includes a chassis with an interconnecting backplane for allowing the addition and removal of different modules as they are needed. Each system module (e.g. WAP accelerator, SMS module, Page module, Mobile IP module, TSL/WTSL Accelerator, Multimedia Accelerator) is a fully working product that supports one particular function. A common bearer module supports all wired network interfaces such as Ethernet, ATM, Frame Relay, ISDN and more, as well as all wireless protocols including GSM, GPRS, SMS, Paging and more. A common database stores user and system information. A central manager manages all system modules, communications among them, and regular health check-ups. A wireless gateway preferably further includes a dedicated WAP engine that offloads the WML encoding and decoding functions from the CPU.

Abstract: A novel design concept for a torquer motor is useful for stabilizing apparatuses in a vibrating structure. According to one aspect, a novel design for a coil pair is provided. A first coil in the pair is box shaped with a hollow interior portion and windings provided on a surface opposite the hollow interior. A second coil in the coil pair is flat and torus shaped with windings provided on the surface. According to one example, the second coil is bent so as to conform to the shape of the first coil, and disposed over the first coil so that the respective windings are oriented orthogonally to each other in a common plane direction so as to define an active area. The active area may be further disposed in the magnetic field of a magnet pair in a torquer motor application. The design provides advantages such as inherent rigidity and more efficient heat transfer, while providing high torque or a desired range of movement.

Abstract: A device for data stream analyzing that is able to recognize different data streams and then start processors or functionalities to store or check data in a data stream. The device includes a processor means and a program memory, making it possible to parse a data stream in a way that is controlled by an interchangeable program. There will be no need for changing the hardware. This could save time and money for companies responsible for providing, maintaining and updating network switches. The device also includes a multiplexable data stream delayline for receiving the data streams, and multiplexing means for connecting different parts of the data stream to the processor means.

Abstract: A Hardware MAC (Media Access Control) unit implements time-critical functions according the 802.11 standard for telecommunications, thereby enhancing system performance. The MAC layer includes three sub-layers: MLME (MAC Sublayer Management Entity), which connects the MAC unit with the host CPU, FTM (Frame Transition Manager), which connects the MAC unit with the network, and FLPM (Frame Level Protocol Manager), which internally connects the MLME sub-layer with the FTM sub-layer. In particular, the FLPM manager includes time-critical and non-time-critical functions that are customarily implemented in software on the MAC by a MAC CPU (Central Processing Unit). The hardware MAC implements time-critical FLPM functions in hardware on the MAC and implements non-time-critical FLPM functions in software on the host CPU so that requirements for processing software on the MAC preferably may be altogether eliminated or alternatively may be substantially reduced.

Abstract: A debugging system and debugging techniques for configurable processors remove the requirement of foreknowledge of specific configurable processor information from components of the debugging system where obtaining that foreknowledge is costly. The system is part of an environment that generates a processor where the proper information is generated in the right forms for such use.

Abstract: The invention relates to a scheduler method and device for handling output queues in a switch. The invention incorporates a number of co-operating techniques such as weighted and deficit driven round-robin and interleaving. The invention provides a scheduling method in a switch in which an input data stream is received and stored in a number of output queues, the method comprising the steps of: polling all queues in order; if the polled queue contains data, refilling a deficit value indicating a maximum amount of data that may be sent from this queue; if the deficit value permits, sending data, and decreasing the deficit value a corresponding amount for the polled queue, else disabling the queue; if any queue is permitted to send after all the queues have been polled, going to a local round, else start polling the first queue of the order again. The invention enables e.g. priority treatment of queues, fairness with regard to varying packet lengths and avoids burstiness.

Abstract: A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Abstract: A highly intelligent DSP load management system is described herein for enhancing the processing capabilities of an SOC device. The DSP load management system enables parallel processing of data at high frequency and distributes, reads and writes data to several CPUs and/or DSPs in the same clock cycle. In addition, the DSP load management system provides forward looking real-time evaluation of arriving data and diverts tasks from one DSP to another, with short or zero latency. The DSP load management system is interfaced between one or more CPUs, one or more DSPs and/or a memory management system for enabling parallel processing of data at high frequency.

Abstract: A garment facility produces custom-made garments according to the body contour and the fit preferences of a customer. Marked pieces designed by a tailor are recorded, along with inspection marks, and sent to a cutting machine as digital design data. The inspection marks in the digital design data are used to ensure proper cutting of the custom-made garment pieces. The completed custom-made garment is also inspected using the inspection marks.