Abstract: Imaging members useful in electrostatographic apparatuses, including printers, copiers, other reproductive devices, and digital apparatuses. More particularly, imaging members having a binder of high molecular weight that is included in one or more layers of an imaging member to impart coating consistency and to provide for increased mechanical strength and improved wear.
Type:
Grant
Filed:
August 23, 2006
Date of Patent:
August 3, 2010
Assignee:
Xerox Corporation
Inventors:
Donald J. Goodman, Satish Parikh, Edward F. Grabowski, Kathleen M. Carmichael, David M. Skinner
Abstract: Image processing is performed on a plurality of layers including at least one line display layer or at least one sprite display layer, from which a plurality of attribute data regarding lines or sprites are sequentially read out so as to produce a plurality of display data, which are then written over each other in a buffer memory, so that the corresponding images are displayed on the screen of a display. With respect to overlapped regions at which plural lines or sprites overlap each other, plural display data are written over each other in the buffer memory in accordance with a first-in-first-out principle. In line processing, image data regarding different lines are subjected to alpha blending and are then written into the buffer memory. In sprite processing, image data regarding different sprites are subjected to rendering and alpha blending and are then written into the buffer memory.
Abstract: A method and apparatus of implementing protocol state machines that conserve energy on energy conscious devices is disclosed. Under this method, most of the energy consuming protocol state machine context invocations or operations are aggregated in time and are scheduled at regular intervals. Such an aggregation leads to many contexts executing concurrently in a burst prior to entering a dormant state. Thus, resource usage can reach a predictable rate pattern of idle and active cycles. With such a pattern, it is possible to take advantage of the energy saving features of processors by downshifting the processor clock speed and use of other resources such as peripherals and buses. The intervals are configured to achieve a tradeoff between timely execution and energy consumption. The aggregation operates across two dimensions, namely, multiple instances of a protocol state machine and multiple layers of protocols in a layered architecture.
Abstract: A method of operating a selective catalytic reduction (SCR) system includes detecting at least one of an ammonia level and a nitrogen oxide level within a cross-sectional area of a chamber at a downstream end of a SCR catalyst. The cross-sectional area is divided into sections. Ammonia flow is automatically regulated from an ammonia distribution grid at an upstream end of the SCR catalyst based on at least one of the ammonia level and the nitrogen oxide level detected.
Abstract: A method of reducing a transmission rate includes determining whether a pause has been received. Whether a maximum of an inter-frame spacing (IFS) has been reached is determined if the pause has been received. The inter-frame spacing is increased by a value if the maximum of the inter-frame spacing has not been reached.
Abstract: A method is designed for controlling a power of a laser beam irradiated onto a track of an optical disc for recording of data at a given linear velocity.
Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.
Type:
Grant
Filed:
December 19, 2002
Date of Patent:
April 25, 2006
Assignee:
Intel Corporation
Inventors:
John F. Zumkehr, John L. Bryan, Howard S. David, Klaus Ruff
Abstract: An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.