Patents Represented by Attorney Powell, Goldstein, Frazer & Murphy LLP
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Patent number: 6506500Abstract: A biaxially oriented polyolefin film having more than one layer and made from a base layer and from at least one outer layer. The base layer include a fatty amide and the outer layer include at least 80% by weight of a linear olefin polymer. The film is suitable, for example, for producing a film laminate by melt extrusion of a polyethylene layer.Type: GrantFiled: May 21, 1999Date of Patent: January 14, 2003Assignee: Hoechst Trespaphan GmbHInventors: Wolfgang Rasp, Detlef Klaus Busch
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Patent number: 6500972Abstract: A method of oxidizing trimethylphenol (TMP) to trimethylbenzoquinone (TMBQ) by various molecular sieves containing various transition metals. In this method, TMP, a molecular sieve containing a transition metal in its framework, an oxidant and a solvent are mixed together to form a reaction system. The reaction system reacting at a temperature of about room temperature to 150° C. to obtain TMBQ, and the concentration of TMP is about 5-60% wt.Type: GrantFiled: July 25, 2001Date of Patent: December 31, 2002Assignee: Chinese Petroleim Corp.Inventors: Soofin Cheng, Chia-Lung Tsai, Berryinne Chou, Debasish Das
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Patent number: 6495472Abstract: A method for avoiding erosion of a conductor structure during a procedure of removing etching residues is provided. The method provides a semiconductor structure and the conductor structure formed therein. A cap layer is formed on the conductor structure and the semiconductor and a dielectric layer formed thereon. The dielectric layer and the cap layer are then etched to partially expose the conductor structure. The etching residues are removed with an amine-containing solution and the amine-containing solution is removed with an intermediate solvent to avoid erosion of the exposed conductor structure. As a key step of the present invention, the intermediate solvent comprises N-methylpyrrolidone or isopropyl alcohol and can protect the conductor structure from erosion.Type: GrantFiled: February 21, 2001Date of Patent: December 17, 2002Assignee: United Microelectronics Corps.Inventors: Chih-Ning Wu, Chan-Lon Yang
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Patent number: 6495417Abstract: A method for increasing tolerance of contact extension alignment in a capacitor over a bit line of a dynamic random access memory is disclosed. Firstly, a substrate having a gate, a bit line and a source/drain region is provided and a insulating layer is formed on the substrate. Then, a dielectric layer is deposited on the insulating layer. Moreover, a contact hole is formed by defining and etching the dielectric layer and the insulating layer to expose a portion of the source/drain region. Furthermore, a conductive layer is deposited on the dielectric layer and the contact hole, wherein the etching selectivity ratio of the conductive layer is near the etching selectivity ratio of the dielectric layer. Finally, an electrode of the capacitor is formed by defining and etching the conductive layer, whereby the dielectric layer protects the portion of the electrode that is beneath the dielectric layer from being etched when misalignment occurs.Type: GrantFiled: September 26, 2000Date of Patent: December 17, 2002Assignee: United Microelectronics Corps.Inventors: Yu-Ju Yang, Yi-Min Jen, Kuo-Yuh Yang, Yu-Hong Huang
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Patent number: 6492240Abstract: Performance of the high resistance resistor, which is polysilicon, is improved by treating the surface of the polysilicon layer in mixed signal integrated circuits for ADSL (Asymmetric Digital Subscriber Line) broadband service application. This treated surface of the polysilicon layer will prevent ions in the resistor from out-diffusion when performing an annealing step after forming the resistor.Type: GrantFiled: September 14, 2000Date of Patent: December 10, 2002Assignee: United Microelectronics Corp.Inventors: Shyan-Yhu Wang, Kun-Lin Wu
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Patent number: 6492235Abstract: A method for forming extension by using double etch spacer. The method includes at least the following steps. First a semiconductor substrate is provided. Then, the gate is formed on the substrate. A first spacer is formed on a sidewall of the gate. Then, numerous first ions are implanted in the substrate by a mask of both the gate and the first spacer to form the source/drain region. Then, the second spacer is formed by etching the first spacer, wherein the width of the second spacer is less than the width of the first spacer. Finally, numerous second ions are implanted in the substrate by a mask of both the gate and the second spacer to form an extension.Type: GrantFiled: January 26, 2001Date of Patent: December 10, 2002Assignee: Macronix International Co., Ltd.Inventors: Han-Chao Lai, Tao-Cheng Lu, Hung-Sui Lin
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Patent number: 6492968Abstract: A method for detecting defects when mixed colors among color channels on a liquid crystal monitor is disclosed. The disclosed method utilizes the interference of four channels of red, green, blue and white colors to check whether a detected liquid crystal monitor can normally show the mixed colors. A rectangular channel drawing is shown on a liquid crystal monitor; wherein the most upper left point, the most upper right point, the most lower left point, and the most lower right point are respectively allocated by red, green, blue, and white pixels. Each color channel then extends separately along the diagonal direction and accompanied with color intensity gradually decreasing to obtain an interference diagram that contains several arc stripes on the rectangular drawing. Accordingly, those defective pixels will be clearly indicated in the rectangular channel drawing because they are usually flashing visually.Type: GrantFiled: October 26, 1999Date of Patent: December 10, 2002Assignee: Inventec CorporationInventors: Bin Yuan, Vam Chang, Kuang-Hsin Lin
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Patent number: 6489206Abstract: A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.Type: GrantFiled: March 22, 2001Date of Patent: December 3, 2002Assignee: United Microelectronics Corp.Inventors: Tai-Ju Chen, Hua-Chou Tseng
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Patent number: 6489196Abstract: The present invention provides a method of forming a capacitor in an integrated circuit. The method comprises providing a semiconductor substrate having a conductive layer thereon. The partial conductive layer is removed to form an electrode. A plurality of first dopants are implanted on a surface of the electrode to form a first doped region. Then a plurality of second dopants are implanted into the electrode to form a second doped region below the first doped region. Then the capacitor is formed comprising the electrode. The first doped region and the second region can reduce voltage coefficient as well as increase capacitance of the capacitor.Type: GrantFiled: January 28, 2002Date of Patent: December 3, 2002Assignee: United Electronics Corp.Inventors: Ming-Yu Lin, Hsueh-Wen Wang
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Patent number: 6488269Abstract: A scrubber for removing soluble materials from harmful gaseous effluents with high efficiency and safety is disclosed. By using twice mixes of the scrubbing liquid and the harmful gaseous effluent, the scrubber meets the standards of environmental protection. The scrubber of this invention also prevents the problems of factory safety presented in the conventional fume scrubber. Owing to the high efficiency of the mixing of the harmful gaseous effluent and the scrubbing liquid, the production facilities or processing units need not stop operating once the supply of the scrubbing liquid terminates.Type: GrantFiled: May 29, 2001Date of Patent: December 3, 2002Assignee: United Microelectronics Corp.Inventors: Johnson Chuang, Jackson Chuang
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Patent number: 6486079Abstract: The present invention provides a method for stabilizing low dielectric constant materials in a semiconductor structure. The method comprises providing the semiconductor structure and thereon spinning-on a dielectric layer. After a curing step, the dielectric layer is treated with an aqueous solution containing, for example, ammonium hydroxide. With the aqueous solution, a passivated film formed on the surface of the dielectric layer, such as a polymer layer, can protect the dielectric layer from adsorption of moisture or solvents.Type: GrantFiled: February 21, 2001Date of Patent: November 26, 2002Assignee: United Microelectronics Corp.Inventors: Cheng-Yuan Tsai, Yung-Tsung Wei, Teng-Chun Tsai, Ming-Sheng Yang
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Patent number: 6487114Abstract: A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.Type: GrantFiled: February 28, 2001Date of Patent: November 26, 2002Assignee: Macronix International Co., Ltd.Inventors: Fuh-Cheng Jong, Kent Kuohua Chang
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Patent number: 6486500Abstract: A structure and manufacturing method of LED is disclosed.Type: GrantFiled: January 28, 2002Date of Patent: November 26, 2002Assignee: Epitech Corporation, Ltd.Inventor: Shi-Ming Chen
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Patent number: 6483605Abstract: A method for transforming a source image into a target image with the original resolution N time to the target resolution is disclosed. The original image data of pixels is read and stored for N scan lines and grouped into a series of matrices each including N2 pixels. The matrices are then classified into various matrix types defined previously, wherein matrices with different numbers of original dots are classified as different matrix types. The target image is formed with a plurality of target units each determined based on one corresponding matrix. In general, a target unit is drawn with target dots having a larger total area when its corresponding matrix includes a larger number of the original dots.Type: GrantFiled: December 7, 1999Date of Patent: November 19, 2002Assignee: Destiny Technology CorporationInventors: Ai-Chieh Lu, Fong Lien
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Patent number: 6482739Abstract: This invention relates to a method for decreasing the resistivity of the gate and leaky junction of the source/drain, more particularly, to the method for forming a metal silicide layer at the gate region and the source/drain region by using two times in depositing metal layer. This condition will form a thicker metal silicide layer at the gate region to decrease the resistivity of the gate and will form a thinner metal silicide layer at the source/drain region to decrease defects in leaky junction at the source/drain region. At first, a semiconductor substrate is provided and a MOS is formed on the substrate and a shallow trench isolation is formed in the substrate. The MOS comprises a gate region, a source region, a drain region, and a spacer which is formed on the sidewall of the gate. The first metal layer is formed over the MOS and a oxide layer is formed over the first metal layer. Partial oxide layer is etched to show the first metal layer which is formed on the gate.Type: GrantFiled: February 21, 2001Date of Patent: November 19, 2002Assignee: United Microelectronics Corp.Inventor: Bing-Chang Wu
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Patent number: 6484023Abstract: An apparatus and a control system to communicate with a portable wireless communication device to act as an electronic account book. The system comprises: an information providing dealer to provide a personal bank savings; an information transmission dealer to define the mailbox of a wireless receiving device and to transmit service information from the information providing dealer; a wireless receiving device, such as an electronic account book, to receive formatted information from different information providing dealers, and for checking the authority by its own machine code. When the user of the wireless receiving device asks for a function service, the information providing dealer will communicate with the information transmission dealer and store the related data of the wireless receiving device.Type: GrantFiled: December 14, 1999Date of Patent: November 19, 2002Assignee: Taiwan Paging Network Inc.Inventor: Hu-Mu Chen
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Patent number: 6479372Abstract: A method for forming a hydrophilic surface on a silicon substrate during cleaning step after well implantation comprises providing a silicon substrate and an insulating layer is deposited thereon for mask alignment requirement. A photoresist layer is formed on the insulating layer and then a well pattern is transferred into the photoresist layer to expose partial the insulating layer thereunder the well defined. Next, implants are implanted into the photoresist layer, the insulating layer and the silicon substrate. Then the insulating layer exposed by the photoresist layer is removed and in-situ a native oxide is formed on the silicon substrate thereunder the well defined whereby changes the surface of the silicon substrate from hydrophobic into hydrophilic. A hard skin on the photoresist layer, resulting from implantation, is removed by oxygen plasma ashing and then the surface of the insulating layer and the silicon substrate are cleaned by conventional technologies.Type: GrantFiled: October 17, 2000Date of Patent: November 12, 2002Assignee: United Microelectronics Corp.Inventors: Jimmy Liou, Ching-Fang Chu
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Patent number: 6479317Abstract: The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises the following steps: A substrate is provided that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forming a composite layer on the substrate, wherein the composite layer at least also covers both the sensor area and the transistor area, and the composite layer increases the refractive index of light that propagates from the doped region into the composite layer; performing an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performing a salicide process to let top of the gate, the source and the drain are covered by a silicate.Type: GrantFiled: October 11, 2001Date of Patent: November 12, 2002Assignee: United Microelectronics Corp.Inventors: Chong-Yao Chen, Chen-Bin Lin, Feng-Ming Liu
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Patent number: 6471610Abstract: The present invention discloses a front derailleur for a bicycle to shift a chain via a chain guide between at least two sprockets which are attached on a frame of the bicycle. The front derailleur includes a wire extending through a stopper which is attached on the frame of the bicycle for transmitting a tension. An actuating link is connected to the wire in response to the tension for driving the chain guide to shift the chain between the sprockets. A wire guide is mounted on a seat tube of the frame and connected with the wire between the stopper and the actuating link for straightening the wire substantially parallel to the seat tube, thereby reducing a friction between the wire and the stopper.Type: GrantFiled: June 7, 2000Date of Patent: October 29, 2002Inventors: Ching-Huan Tseng, Yu-Jen Chien
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Patent number: 6468824Abstract: The present invention provides a method for forming a semiconductor device with a metallic substrate. The method comprises providing a semiconductor substrate. At least a semiconductor layer is formed on the semiconductor substrate. A metallic electrode layer is formed on the semiconductor layer. The metallic substrate is formed on the metallic electrode layer and the semiconductor substrate is removed. The metallic substrate has advantages of high thermal and electrical conductivity, that can improve the reliability and life-time of the semiconductor device.Type: GrantFiled: March 22, 2001Date of Patent: October 22, 2002Assignee: Uni Light Technology Inc.Inventors: Nai-Chuan Chen, Bor-Jen Wu, Yuan-Hsin Tzou, Nae-Guann Yih, Chien-An Chen