Abstract: A switching device (22) responsive to an input voltage V.sub.A is powered by low and high internal supply voltages V.sub.L and V.sub.H. The device changes state as V.sub.A -V.sub.L passes a threshold voltage V.sub.T. After the device makes a desired change of state in response to rising V.sub.A, a hysteresis circuit (24) temporarily decreases V.sub.T below that which would otherwise be present. Likewise, after the device makes a desired change of state in the opposite direction when V.sub.A is falling, the hysteresis circuit temporarily decreases V.sub.T. In both cases, V.sub.T later automatically returns to its original value. This dynamic hysteresis prevents spikes in V.sub.L and V.sub.H from causing undesired changes in state.

Abstract: A double-ended code converter (10) contains three or more like-configured amplifiers (T.sub.O -T.sub.M+1). Each has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for receiving a signal to control charge carriers moving from the first electrode to the second. The first electrodes are coupled to a circuit supply (12) which may be a current source or a voltage supply. The second electrodes are selectively coupled to one or the other of a pair of lines (L.sub.B and L.sub.BN) which are coupled to respective load elements (14.sub.B and 14.sub.BN) to provide a pair of complementary signals (V.sub.B and V.sub.BN).

Abstract: An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.

Abstract: A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V.sub.IN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V.sub.OUT) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: A multi-stage amplifier (21, 22, 23, or 24) has three or more amplifier stages (A1, A2, and A3) arranged in a capacitatively nested configuration for frequency compensation. The technique consists of nesting two of the stages together with a pole-splitting capacitor (C1) to form a stable device (21 or 22) and then nesting this device and a third of the stages together with another pole-splitting capacitor (C2) to form the amplifier.

Abstract: A layer of a conductive material consisting of aluminum alone or in combination with a small percentage of copper and/or silicon is formed on a semiconductor surface in a two-step deposition process in such a manner as to largely avoid serious continuity defects in the layer.

Abstract: A bipolar voltage translator contains a pair of differentially coupled transistors (Q1 and Q2) for converting an input voltage (V.sub.IN) supplied to one (Q1) of the pair into an output voltage (V.sub.OUT) taken between the other (Q2) and a first resistor (R9). A further transistor (Q4) coupled through a second resistor (R12) to a V.sub.EE supply provides current for the differential pair. A voltage reference circuit (10) containing at least three serially coupled diodes (S5, J3, and J4) with a resistive voltage divider (R13 and R14) across an intermediate one (J3) of the diodes provides the current-source transistor with a reference voltage (V.sub.REF2) that equals V.sub.EE +(1+.alpha.)V.sub.BE where .alpha. is 0.2-3.0. The ratio of the first resistor to the second is desirably .beta./.alpha. where .beta.is the output voltage swing divided by V.sub.BE. If .beta. is 1 and the transistors are NPN devices, the output voltage level is suitable for current tree logic.

Abstract: A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.

Abstract: A bistable switching circuit contains a pair of like-polarity input transistor circuits (Q1 and Q2) arranged in a differential configuration to receive a corresponding pair of input signals. A pair of like-polarity cross-coupled transistor load circuits (Q3 and Q4) complementary to the input transistor circuits are coupled to them. A pair of resistive elements (R1 and R2) are coupled between a voltage supply (V.sub.CC) and the load transistor circuits. An output transistor (Q5) complementary to the input transistor circuit has its control electrode and one of its flow electrodes coupled across one (Q4) of the load transistor circuits. When the input signals assume values capable of causing the output transistor to turn on, no current flows in the output transistor until regeneration occurs in the load transistor circuits -- i.e., until they switch states.

Abstract: In a memory cell array of the kind including a memory cell capacitor and a memory cell transistor connected in series between a field plate line and a bit line, both the field plate line and bit line are precharged to the same potential level. The field plate line is connected to one input of a sense amplifier and the bit line is connected to the other input. The charge and discharge of the memory cell capacitor causes equal and opposite voltage changes on the field plate line and bit line. With respect to prior art the cell signal is increased by the amount of signal on the field plate line and when sensed against a reference signal which is about one-half the amount of the cell signal, the sensed signal is about twice that obtainable in the prior art.