Abstract: A storage system is provided for storing data for a computer system where the storage capacity can be incrementally increased without disrupting the operations of the storage system. The storage system comprises a base unit, and a plurality of modular units. The modular units are inserted into the system as increased storage capacity is required. Each modular unit has an enclosure comprising top, bottom, and side walls. The bottom and top walls each have at least one power connector and data transmission connector. The bottom wall of a first modular unit enclosure attaches to the base unit enclosure and the top wall of the first modular unit enclosure can attach to the bottom wall of a second modular unit enclosure. At least one back plane is provided in each modular unit for providing attachment for a set of storage devices.

Abstract: A method and system for providing a voltage-sensing preamplifier for use with a magnetoresistive sensor is disclosed. The method includes providing a gain stage and providing a control circuit. The system includes the gain stage and the control circuit. The gain stage includes at least one input device that is coupled with the magnetoresistive sensor through an interconnect having a characteristic impedance. The at least one input device has a first input impedance. The control circuit provides at least one signal to the at least one input device. The at least one signal controls the first input impedance of the at least one input device to control a second input impedance of the voltage-sensing preamplifier, such that the preamplifier input impedance is modified toward the characteristic impedance of the interconnect to improve the bandwidth of the signal amplified by the system.

Abstract: Method and system aspects for nulling output offset current in an amplifier are described. In an exemplary method aspect, the method includes determining at least one offset value with a power amplifier in at least one mode. The at least one offset value then utilized to identify an output offset current value in the power amplifier. An adjustment to an input signal to the power amplifier occurs until the output offset current value is substantially nulled to identify a power amplifier offset value.

Abstract: A preamplifier circuit to improve the ESD immunity of magnetic recording devices having magnetoresistive (MR) sensors, without degrading the sensor's high-frequency characteristics. The preamplifier circuit is coupled to an MR sensor having one terminal grounded. The preamplifier circuit includes a varistor coupled between a power supply line and a ground terminal. If a high voltage, exceeding the varistor voltage, is applied to the chassis (ground), it is discharged through the varistor between the power supply voltage line and the ground terminal, instead of through the MR head or the arm electronics module. The present invention thereby protects the MR head and the arm electronics module from ESD damage.

Abstract: In a storage system comprising an array of storage devices, including a processor and memory, a plurality of logical tracks are organized on the storage devices in segments comprising columns striped across the storage devices. A system and method are provided for storing logical tracks in the storage devices. Sequentially logically related logical tracks are stored together in neighborhoods. Logical tracks of the same neighborhood A0 destaged at the same time are assigned to a single open segment with other logical tracks of the same neighborhood type. The time at which open segments are designated as closed segments to be written to the storage devices is based on performance, disk utilization and memory utilization criteria. Logical tracks are never split between segment columns. Also, attempts are made not to split a neighborhood of logical tracks being destaged together between segment columns.

Abstract: The present invention provides a method and system for translating a signal from a chip with a negative substrate bias. The method and system includes receiving an input signal in a first state in a first logic level, the first state being approximately at ground; and translating the input signal to a second state in a second logic level, the second state being above ground. The method and system translates a signal from a chip with a negative substrate bias. In the preferred embodiment, the method and system of the present invention uses a translation circuit to translate and drive the signal off-chip. The translation circuit in accordance with the present invention functions with a positive Vcc and a Vee lower than ground, and also does not violate any of the rules of functionality for components used in a chip which has a negatively biased substrate and a voltage limit on its components.

Abstract: A PLL circuit and a phase locking method for rapidly phase locking a sample signal to a target clock. The phase locked loop (PLL) circuit comprises: a voltage controlled oscillator; an error correction logic circuit for determining a phase difference between a signal output by the voltage controlled oscillator and a target signal; and a controllable variable delay circuit for determining a delay of the signal output of the voltage controlled oscillator instantly on the basis of an initial phase difference that is determined by the error correction logic circuit.

Abstract: A method and apparatus for serializing access to disk arrays shareable among a plurality of RAID control units at a substantial reduction in intercontrol unit communication by (a) defining a lock function over the parity image blocks at each of the disk drives of a shared disk array; and (b) executing a path expression at each accessing control unit, the path expression includes requesting a lock from the drive on the parity image and enforcing a busy-wait until a lock is granted, executing the RAID function, and then releasing the lock.

Abstract: The present invention provides a system, method and data format wherein a redundant sync byte or group of sync bytes is provided in a data sector at a distance sufficient to isolate the redundant sync byte from the primary sync byte in the event of multiple byte defects. In a first embodiment, a redundant sync byte, or group of sync bytes, is provided in the AGC field preceding the primary sync region. Upon failure to detect the primary sync byte, an attempt is made on a subsequent revolution to read the secondary sync byte, either by holding the AGC gain prior to reaching the data block, or initiating an “early read” just prior to reaching the data block. In a second embodiment of the invention, the redundant sync byte is provided within the data field subsequent to the primary sync region. On failing to detect the primary sync byte, the secondary sync byte can be read immediately or can be postponed until a subsequent revolution.

Abstract: A method and apparatus for managing update writing in place in linear address space mapped memories. This is attained by partitioning the memory into compressed and uncompressed areas, estimating the percent of compressible images of fixed-length symbol strings recordable into the image locations, revising the estimate upward or downward as a function of the persistency of runs of writes to one area or the other, and adjusting the relative number of locations in the areas proportionally to the revised estimate.

Abstract: A cleaning apparatus for cleaning sensitive components such as those used in the disk drive and semi-conductor industries. The cleaning apparatus of the present invention includes of an adhesive tip mounted on a handle. The adhesive tip may be fixedly or rotatably mounted on the handle, and is further comprised of an adhesive film which may be wrapped about the handle or formed over a more compliant or more resilient surface. The adhesive film is preferably a low residue, low out gassing material which may easily remove particles from the surface of precision components without further contaminating the component.

Abstract: An FPC cable which is excellent in noise resisting property, manufacturing cost, mounting operability to a carriage, and maintenance. The FPC cable includes a spacer and a reinforcing plate. In the patterned surface of the FPC, a head pad to which a head wire is bonded is formed on a pad forming portion and a preamplifier chip is mounted on a device mounting portion. Wiring patterns are linearly connected between the head pad and the preamplifier chip and between the preamplifier chip and an I/O-side end portion, respectively. In the spacer, a cavity is formed for storing the preamplifier chip. The reinforcing plate is inserted into the space formed by folding back the pad forming portion, and the spacer is engaged with the device mounting device, thereby constituting a magnetic-head-side end portion.

Abstract: In a storage system comprising an array of storage devices including a processor and memory, a plurality of data blocks are organized on the storage devices in segments striped across the storage devices. A main directory, stored in memory, contains the location on the storage device of each of the data blocks. For each segment a segment directory having information on the data blocks in the segment is stored on the storage devices. When a damaged segment directory is detected, a checkpoint of the main directory is written to the storage devices. A list is maintained of damaged segment directories such that segments on the damaged segment directories list are not garbage collected. Following a main directory recovery procedure, the damaged segment directories are reconstructed using the main directory.

Abstract: The present invention provides an actuator locking mechanism which is structurally simple and has a strong locking force. The actuator locking mechanism has an actuator on which a slider having a transducer mounted thereon for transferring information between the transducer and a storage medium is mounted and which is driven so that the element scans the storage medium, an attracting member which is magnetically attractable with at least a portion of the actuator when the actuator is driven so that the slider is moved to a non-recording region of the storage medium, a support member on which the attracting member is mounted and which is rotatably attached to the base, and a spring which is engaged with the support member and gives elastic force to the support member so that the actuator attracted magnetically to the attracting member is given force in a direction where the slider is directed from the recording region of the storage medium to the non-recording region.

Abstract: The present invention provides a system, method and data format wherein a redundant sync byte or group of sync bytes is provided in a data sector at a distance sufficient to isolate the redundant sync byte from the primary sync byte in the event of multiple byte defects. In a first embodiment, a redundant sync byte, or group of sync bytes, is provided in the AGC field preceding the primary sync region. Upon failure to detect the primary sync byte, an attempt is made on a subsequent revolution to read the secondary sync byte, either by holding the AGC gain prior to reaching the data block, or initiating an "early read" just prior to reaching the data block. In a second embodiment of the invention, the redundant sync byte is provided within the data field subsequent to the primary sync region. On failing to detect the primary sync byte, the secondary sync byte can be read immediately or can be postponed until a subsequent revolution. The missed first data region is reconstructed using ECC information.

Abstract: A method and apparatus for writing binary servo data into the servo bursts contained on the storage medium of a storage device. The binary servo information may include track identifying information such as a track number, cylinder number, head number, sector number, index and/or SID. A burst includes T time slots, each slot comprising one cycle of the servo burst frequency, and the servo data to be written comprises X bits of binary data. Each one-bit of the servo data is represented as a slot containing a transition, and each zero-bit is represented as an empty or null slot. In this manner, the present invention provides a highly bit-efficient scheme for representing digital servo data. A high quality PES signal is assured by writing the binary servo information in such a manner as to guarantee a threshold number of transitions per burst as required for accurate peak-hold detection.

Abstract: A disk drive and a method for controlling the disk drive in which an additional read from a medium can be performed as needed while minimizing the command overhead to the minimum. In a disk drive device 10, even if a read command is issued, and all the required data is stored in the cache memory such that the data transfer can be performed without the intervention of a local MPU 16, a HIC 15 performs the data transfer so as to leave the last one block and waits for the intervention of the local MPU 16. The local MPU 16 provides instructions to transfer the last one block when the preparation for the command termination is completed, and if a plurality of blocks of data to be transferred are remaining when the local MPU 16 instructs the HIC 15 to transfer the last one block, the HIC 15 executes all the data transfer without stopping the data transfer before the last one block, completing the command.

Abstract: A data recording disk drive is provided with a reassignment architecture that employs both an "in-line" approach for small disk defects and an "off-site" reassignment for multiple-sector defects. As a further aspect of the invention, the defective sites that have been off-site reassigned are periodically reinspected to determine whether they in fact remain defective. If it is determined upon inspection that the defect is no longer present, the data in the off-site reassign area is returned to its original location, freeing spares for reuse. As a further aspect of the invention, reinspection is performed at disk drive spin-up or during idle periods.

Abstract: An electronic circuit apparatus is provided comprising a component disk drive, and an electronic circuit implementing the component drive for local storage as an alternative to costlier solid state memory, wherein the electronic circuit has at least one function not related to the operation of the component disk drive, and wherein the electronic circuit uses information stored on the component disk drive to perform the non-storage related function. The apparatus is suitable for a plurality of electronic devices and for electronic circuit applications residing in a card enclosure adapted for plugging into an electronic device or computer. In the preferred embodiment, the component disk drive comprises a disk with a single recording surface mounted directly to a flat motor, a low profile actuator assembly including a single suspension supporting an MR head, and means for "parking" the head at the center of the disk.