Abstract: A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.

Abstract: The charge pump circuit of a phase locked loop has a sensing device, latch and charge pump. When there are contemporaneous up and down signals being produced by the charge pump, a reset signal is provided from the sensing device to a latch which is coupled between the input to the circuit and the pump. Input signals are then inhibited from reaching the charge pump.

Abstract: A DRAM is operated based upon an external clock input, a column enable, and a row enable. The DRAM is accessed and row and column addresses are latched into buffers based upon the clock input.