Abstract: A semiconductor nonvolatile memory cell comprised of a p-type silicon well 12, an n+ drain 8 and an n+ source 10, the source and the drain regions defining an channel region 7. On top of the well 12 there are laminated a thin silicon dioxide film 2 served as a gate oxide, a polysilicon layer 32 and a SrTiO3 layer 34 comprised of a high dielectric substance, in respective order. Further on top of these layers, there is formed a polysilicon layer 36 served as gate electrode. By using the memory cell and appropriate select transistors, a semiconductor nonvolatile memory device is constructed.