Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Abstract: A method for fabricating a field emission display and the resulting display device are disclosed. The method includes the steps of arranging a sealing layer between a face plate and a substrate, heating the sealing layer until the substrate layer adheres to the face plate, and then pulling the face plate away from the substrate so that the vacuum is improved. The sealing layer may be constructed from glass and heated with a heating coil made from Ni-chrome wire. The elements can be positioned using industrial robots using common manufacturing techniques.

Abstract: A method for selecting a set of test cases which may be used to test a software program product is disclosed. The program to be tested may have a number of code blocks that may be exercised during execution of the program. The method includes identifying each of the code blocks that may be exercised, and determining a time for executing each of the test cases in the set. A set of the test cases is then selected that exercises a maximum number of the identified code blocks that can be exercised in a minimum time. The selection step may be performed by executing a genetic algorithm for determining which subset of test cases to use, using a combination of time and coverage as a fitness value.

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Abstract: A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.

Abstract: Integrated circuit fabrication with a thin layer of oxynitride atop the interlevel dielectric, to provide an etch stop to withstand the overetch of the metal layer.

Abstract: A semiconductor integrated circuit to determine a passage of time that may include a time during which no electrical power is supplied to the circuit is disclosed. The circuit has a timing device that includes a memory storage dielectric material for trapping charge carriers and releasing the trapped charge carriers in a known manner over time. The timing device has an electrical parameter that is relatable to an electric field created by the trapped charge carriers. A charge injection circuit is provided for selectively injecting charge carriers into the memory storage dielectric material to create an initialized state, and a time reader circuit determines when the electrical parameter has reached a predetermined value that corresponds to a passage of a predetermined time. Preferably the timing device is an insulated gate field effect transistor in which the memory storage dielectric material is a dielectric material, such as SONOS or SNOS, between the gate and channel overlying at least the channel area.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: Signal propagation times in circuit paths are matched to compensate for signal delays due to differences in the physical parameters, such as lengths, of the circuit paths. This is accomplished by adjusting the length of lead lines and by the addition of resistors in series with shorter lead lines in a chip or die. In a chip with an active device, such as logic, having multiple input lines, the lines are divided into long lines and short lines. All long lines are laid out so as to have the same length and to use the least amount of chip surface area. Similarly, all short lines are laid out on the chip so as to have the same length while using the least amount of chip surface area. With all the short lines having the same propagation time difference relative to all the long lines, the same resistive element is added to all the short lines to effect the same RC delay in signal propagation on the short lines so as to match the signal propagation time on the short lines with that on the long lines.

Abstract: An integrated circuit package has leadless solderballs attached to the substrate with a conductive thermoplastic adhesive. The leadless solderballs are preferably made with a copper-nickel-gold alloy. The conductive thermoplastic is preferably of the silver fill type. The integrated circuit package is placed in a frame and held to the printed circuit board with a clamp or with a screw.

Abstract: A complementary-metal-oxide-semiconductor, static-random-access-memory cell has two pairs of n-channel and p-channel transistors in complementary symmetry, push-pull arrangement. One pair of complementary transistors stores the binary state of the memory cell, and the other pair of complementary transistors stores the complement of the binary state of the memory cell. Both transistors in each of the complementary pairs of complementary transistors in the memory cell have nearly equal current carrying capacity and provide a voltage trip point for a change of state of the memory cell equal to approximately 1/2 the bias voltage across the memory cell. Complementary word lines and bit lines select a memory cell for reading or writing. The wordline control gates have complementary transistors, and those complementary transistors push or pull current to the memory cell in parallel to minimize the effect of transistor threshold voltage on the flow of current to the complementary transistors in the memory cell.

Abstract: An integrated circuit includes test circuitry and test mode enable circuitry. During power-up, an over-voltage on a package pin of the integrated circuit can initiate a test mode. The test mode enable signal may be latched into its activity state by a signal provided on a second package pin. Thereafter, the first and second package pins may be used in the normal voltage range during the test operations.

Abstract: An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at static random access memory (SRAM) speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: In a method for aligning a rotor of a polyphase dc motor in preparation for starting the motor. a first energization signal is applied to field coils of the motor in a first predetermined phase for a first predetermined time. Then, a second energization signal having a second predetermined phase displaced from the first phase by a predetermined amount is applied to the field coils for a second predetermined time period. In one embodiment, the second energization signal is applied to produce a maximum torque upon the rotor when the rotor is positioned at a location determined by the first energization signal. In the case of a three phase motor, the second energization signal is displaced by two commutations from the first energization signal.

Abstract: A circuit and method for operating a polyphase dc motor of the type having a plurality of driving coils connected together at a center tap current input node. Each driving coil have a current input node at an end opposite the center tap connection. A plurality of pairs of switches are arranged for connection in series across a power supply voltage. Each pair have a connection node between each switch connected to a respective one of the current input nodes. A sequencer individually operates the switches to cause a driving current to be passed between sequentially selected only single ones of the driving coils and the center tap current input node.

Abstract: A method and circuit for operating a polyphase dc motor having a plurality of driving coils is presented. In one of the available operating modes, drive current supplied to the driving coils is chopped, in PWM fashion to control the maximum current delivered thereto by turning the drive current on and off. Zero crossings of a back emf voltage of the driving coils that are connected into a floating state are detected for producing a commutation signal, and the detection of zero crossings is inhibited for a predetermined time after the drive current is turned off during the chopping step to avoid detecting a false zero crossing. In normal operation, detected back emf sampled voltages are forwarded to back emf detection circuitry responsive to a high frequency clock.

Abstract: A circuit for operating a polyphase dc motor that has a plurality of driving coils has circuitry for receiving the back emf of at least one of the driving coils at a time when the at least one of the driving coils is in a floating state prior to the desired commutation sequence. Circuitry is provided for determining an anticipated direction the back emf will cross a reference voltage based upon the desired commutation sequence. And circuitry is also provided for determining if the back emf received by the circuitry for receiving the back emf crosses a reference voltage from other than the anticipated direction.In addition, a method for operating a polyphase dc motor having a plurality of driving coils includes determining the actual instantaneous position of the rotor of the motor by determining when the back emf of at least one coil at a time when the at least one coil is in a floating state prior to the desired commutation sequence crosses a reference voltage from a predetermined direction.

Abstract: In a disk drive, the read-write heads of the disk drive should be parked during a power failure. The kinetic energy of the spinning rotor is used to move the head away from the disk's surface. A high voltage is produce from the low voltage spindle motor by using a BEMF voltage to step up the voltage in a voltage supply capacitor to a higher voltage by enabling or disabling a switch connected to a comparator. When the switch is turned on, it shorts the rectified voltage in the stator windings to ground in order provide a current path for a current formed in the coils by the BEMF. When the current reaches a predetermined level, the switch is turned off. The current flows through the voltage supply capacitor so that its voltage is "kicked-up" by the inductance of the windings and by the BEMF still present in the stator windings. This increased voltage is used to park the heads and to brake the motion of the spindle. Two control feedback loops are used to more efficiently enable the voltage conversion.

Abstract: A transconductor circuit has first and second half cascode mirror circuits. Each half cascode mirror circuit has a cascode transistor, an active transistor, a base current compensating transistor, and a current source connected at one side to a supply voltage and at another side to the cascode transistor. The cascode and active transistors are connected in series between the current source and a first reference potential node. The base current compensating transistor is connected between the supply voltage and the base of the active transistor, and has its base connected between the current source and the cascode transistor. The bases of the cascode transistors of the first and second half cascode mirror circuits are connected to a second reference potential. First and second output mirror circuits are connected to mirror a current in a respective active transistor of the first and second half cascode mirror circuits.

Abstract: A programmable protection circuit comprises three identical units connected between a common point (C) and a first conductor (A), a second conductor (B) and ground (M). Each unit comprises the anti-parallel arrangement of a thyristor (T) and a diode (D), a bipolar transistor (TR) being connected between the gate and anode of the thyristor, the anodes of the thyristors being connected to the common point and the base terminal of each unit constituting a programmation terminal and being connected to a device defining a voltage threshold. Each device defining a voltage threshold is a zener diode (Z1, Z2, Z3) connected between each base terminal and the common point.