Abstract: A system and method for implementing a hierarchical policy for computer system administration which is extremely flexible in assigning policies to managed objects. Policies are defined to be rules for the values of the attributes of managed objects. Policy groups comprise the basic building blocks and they associate a set of policies with a set of managed objects. Policy groups can also be members of other policy groups and a policy group inherits the policies of its parent policy groups supporting the hierarchical specification of policy. A given policy group may have multiple parents which allows the "mix-in" of policies from the parents. Cloning and templates in conjunction with validation policies and policy groups provide standardization and a concomitant reduction in system administration complexity.

Abstract: A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.

Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture.

Abstract: A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.

Abstract: A redundant array storage system that can be configured as a RAID 1, 3, 4, or 5 system, or any combination of these configurations. The invention comprises a configuration data structure for addressing a redundant array storage system, and a method for configuring a redundant array storage system during an initialization process. The redundant array storage system comprises a set of physical storage units which are accessible in terms of block numbers. The physical storage units are each configured as one or more logical storage units. Each logical storage unit is addressed in terms of a channel number, storage unit number, starting block number, offset number, and number of blocks to be transferred. Once logical storage units are defined, logical volumes are defined as one or more logical storage units, each logical volume having a depth characteristic. After the logical volumes are defined, redundancy groups are defined as one or more logical volumes.

Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture.

Abstract: A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151, . . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160).

Abstract: An N-channel SNOS or SONOS type memory array (100) has programmable states with a negative, depletion mode threshold lower in magnitude than the supply voltage V.sub.CC when erased and a positive threshold when programmed. During reading, the supply voltage V.sub.CC is applied to the drain (16), while a positive voltage V.sub.R less than V.sub.CC -V.sub.ds,sat is applied to the source (14), where V.sub.ds,sat is the saturation voltage of the device. A reference voltage may also be applied to the substrate (11) during a read operation. Selected devices have V.sub.R applied to the gate (12), while inhibited devices have ground or the substrate potential V.sub.SS applied to the gate (12).

Abstract: A device for rotating a first structure relative to a second structure has a rotatable shaft for attachment to the first structure. A first cylinder is coaxially attached to the rotatable shaft, and has a plurality of bearing constraining apertures for holding a plurality of bearings. A hollow fixed member for attachment to the second structure has a coaxially attached second cylinder outside of the first cylinder. The second cylinder has a plurality of bearing seats on its inside wall for selectively receiving the bearings. The number of bearing constraining apertures is different from the number of bearing seats, so that the bearings are harmonically aligned by the constraining apertures to be movable to within the bearing seats only at selected progressive locations. A handle is coaxially and rotatably mounted to the fixed member, and carries a cam inside the first and second cylinders.

Abstract: A method and apparatus for compensating for weak elements of a dynamic memory circuit on an integrated circuit chip is disclosed. The method includes identifying weak elements in the memory circuit. The elements may be identified by a known test program, and may be bits, blocks, or other portion of a dynamic memory circuit. The locations of the identified weak elements are programmed into a programmable memory, and the programmed information in the programmable memory is used to refresh the identified weak elements at a different rate from the refresh rate of other bits. This allows an extended or longer refresh interval to be used for the strong elements, while providing adequate refresh for the weak elements, thereby reducing the refresh interval required for the overall memory circuit from the refresh interval which normally would have been used.

Abstract: A computer storage system having a dual port buffer memory for improved performance. The invention comprises a computer storage subsystem that includes a dual port buffer memory that effectively provides two internal data busses for the storage subsystem: one bus for data transfers between the dual port buffer memory and the storage units, and a second bus for data transfers between the dual port buffer memory and a CPU. The throughput of the storage subsystem is roughly equivalent to the bandwidth of the slower of the two busses. In alternative configurations, the invention may use a plurality of dual port buffer memories in parallel to increase the effective throughput of the storage subsystem, and better match the bandwidth of the two busses.

Abstract: A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit.

Abstract: A method for on-line restoration of redundancy information in a redundant array storage system. The invention provides alternative methods of restoring valid data to a storage unit after a Write failure caused by a temporary storage unit fault. In the first preferred method, a valid redundancy block is generated for the corresponding data blocks on all storage units. Resubmitting the interrupted Write operation causes the old (and potentially corrupted) data block to be "subtracted" out of the re-computed redundancy block. The uncorrupted new data block is written over the old data block, and is "added" into the re-computed redundancy block to create a new, corrected redundancy block. The new, corrected redundancy block is written to the appropriate storage unit. In the second preferred method, a new redundancy block is generated from all valid data blocks and the new data block. The new redundancy block and the new data block are then written to the appropriate storage units.

Abstract: A single address register control technique for a memory controller allows both cache "reads" and page-mode "writes" to be implemented without requiring separate hardware address registers for each function. Because both functions may be implemented with virtually no performance loss in a high performance memory system using a single address register, a comparator, and one additional register, the costs and other disadvantages inherent in otherwise replicating control registers are obviated.

Abstract: A rotary drive apparatus has a drum with a first plurality of generally parallel grooves spaced a predetermined distance apart. A capstan adjacent the drum has a second plurality of generally parallel grooves spaced the same predetermined distance. The capstan may be disposed adjacent the drum with its grooves disposed between the grooves on the drum. The drum and the capstan may have parallel axes of rotation. A continuous cable in the grooves of the drum and the capstan couples the drum and the capstan for joint rotation. A pulley and spring adjacent the capstan tension the continuous cable.