Abstract: A semiconductor device structure (10) includes similar devices (30), (32), and (34) having different operating characteristics. Each similar device is formed on a semiconductor substrate layer (14) through openings (16), (18), and (20) in a mask layer (12). Each opening (16), (18), and (20) has a different feature size and spacing that allows for various thickness levels of layers within the similar devices (30), (32), and (34) due to desorption from the mask layer (12). The growth rate within each opening (16), (18), and (20) is inversely proportional to the feature size of the respective opening.

Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.

Abstract: A transistor device (10) includes an epitaxial layer (14) formed on a semiconductor substrate layer (12). A base layer (16) is formed on the epitaxial layer (14) and a source layer (18) is formed on the base layer (16). A trench region (22) is formed extending through the source layer (18), the base layer (16), and the epitaxial layer (14) and into the semiconductor substrate layer (12). An oxide layer (24) is formed on the source layer (18) and on the internal walls of the trench region (22) such that the oxide layer (24) is wider at the bottom of the trench region (22) than at the top in order to handle high voltage applications. A gate layer (26) is formed within the trench region (22) on the oxide layer (24). The gate layer (26) causes a drift region formed within the epitaxial layer (14) to fully deplete under full rated blocking conditions, decreasing the drift region component of the on-resistance which is the dominant parameter in very high voltage devices.

Abstract: This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50,52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 , over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

Abstract: A digital to analog converter (10) and method is provided in which a plurality of digital to analog converter cells (16) generate an analog output signal based on a digital input signal, the cells being characterized by a switching threshold. An error signal circuit (22) generates a control voltage signal for controlling a first variable delay register (12). Signals latched by the first variable delay register (12) are characterized by rising and falling edges, and the first variable delay register (12) is controlled by the control voltage signal such that the rising and falling edges cross the switching threshold at substantially the same time.

Abstract: Generally, and in one form of the invention a semiconductor device is presented comprising: a transistor comprising an emitter finger and a base finger; and a ballast impedance connected to the base finger. Other devices and methods are also disclosed.

Abstract: In a process for creating a mask on the surface of an integrated circuit workpiece, a first layer of resist is applied to the surface of the workpiece. An upper portion of this first layer is metallized. A second layer of photoresist is applied to the first layer. The second layer of photoresist is selectively exposed and developed. Using the developed second layer as a mask, exposed respective areas of the metallized upper portion of the first layer are etched, and the non-metallized portions of the first layer are subsequently etched. The result is a metallized mask on the surface of the workpiece that avoids the problems of high topographical relief and irradiation reflections from the workpiece surface.

Abstract: This is a method of forming a semiconductor-on-insulator water with a single-crystal semiconductor substrate.

Abstract: A method and apparatus are provided for holding and positioning objects for a single diamond point turning operation. The objects which may include liquid phase epitaxy films are mounted on multiple platforms (10, 46). The platforms (10, 46) are securely connected to a base (20). The platforms (10, 46) are positioned, independently from one another, for elevation and orientation relative to the base (20) while the platforms (10, 46) are securely connected to the base (20).

Abstract: A GaAs field effect transistor with a source contact including both an ohmic contact and a Schottky barrier, the Schottky barrier between the ohmic contact and the gate, is disclosed. The Schottky barrier provides a high frequency source contact close to the active channel and thereby reduces the parasitic source resistance at microwave and higher frequencies.

Abstract: A method of forming an n-p junction in a body (44, 44a, 44b) formed of Group II and Group VI elements. The body (44, 44a, 44b) initially is of p-type conductivity characteristic, and a dry reactive etching process is employed for forming a via (60, 60a, 60b) in the body by a chemical reaction which is also effective to type convert a portion of the body adjacent the via. An n-doped region (64, 64a, 64b) is thereby formed within the body around the via and between the via and the remaining, p-doped region of the body, thereby defining an n-p junction. In one embodiment, the body is mounted on an electrical device (50, 50a, 50b) having an input contact pad (58, 58a, 58b), and an electrically conductive layer (62, 46a, 90) is formed in connection with the contact pad and the n-doped region adjacent the via.

Abstract: This is a method of forming an array of electron emitters at the face of a semiconductor layer. The method comprises the steps of depositing a layer of polycrystalline silicon on a face of a semiconductor workpiece; doping the polycrystalline silicon layer to render the polycrystalline silicon layer conductive; and for each of a plurality of emitter cells, performing an orientation-dependent polycrystalline silicon etch to define a pyramid for the cell having a base affixed to the workpiece and an upstanding tip opposed to the base. Preferably the method also includes the steps of forming a field effect transistor at the face of the workpiece prior to the depositing of the layer, with the pyramid having a base in conductive contact with the drain of the transistor. The polycrystalline silicon layer may be doped in situ after deposition.

Abstract: A system and method for epitaxial growth of high purity materials on an atomic or molecular layer by layer basis wherein a substrate is placed in an evacuated chamber which is evacuated to a pressure of less than about 10.sup.-9 Torr and predetermined amounts of predetermined precursor gases are injected into the chamber from a location in the chamber closely adjacent the substrate to form the atomic or molecular layer at the surface of the substrate while maintaining the pressure at less than about 10.sup.-9 Torr in the chamber in regions thereof distant from the substrate. The precursor gases are provided from a plurality of tanks containing the precursor gases therein under predetermined pressure and predetermined ones of the tanks are opened to the chamber for predetermined time periods while maintaining the pressure in the tanks. A dose limiting structure is provided for directing predetermined amounts of the precursor gases principally at the substrate with a dose limiting directional structure.

Abstract: An improved pyroelectric material comprises a polycrystalline material doped with at least one donor element such that the polycrystalline material has a grain size less than 10 .mu.m (or 5 .mu.m) and a Figure of Merit greater than 90 nC/(cm.sup.2.K). In the preferred embodiments the polycrystalline material is barium strontium titanate or calcium-substituted barium strontium titanate. The donor element may be Nb, Ta, Bi, Sb, Y, La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er or a combination thereof. The material may additionally be doped with an acceptor such as Co, Cu, Fe, Mn, Ru, Al, Ga, Mg, Sc, K, Na, U, In, Mg, Ni, Yb or a combination thereof to control the resistivity. Other structures and methods are also disclosed.

Abstract: A tantalum pentoxide substrate 34 immersed in a liquid ambient (e.g. 10% hydrofluoric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the Ta.sub.2 O.sub.5 substrate 34. An etch mask (e.g. organic photoresist 32) may be positioned between the radiation source 20 and the substrate 34. The Ta.sub.2 O.sub.5 substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the Ta.sub.2 O.sub.5 is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.

Abstract: A system and method for testing the properties of semiconductor material including an enclosed chamber, a sample of semiconductor material under test having a polished surface portion and insulator layer over the polished surface portion supported in the chamber, a spring probe disposed within the chamber impinging against the insulator layer, a contact disposed on a surface portion of the semiconductor material under test, a pair of contacts disposed external to the chamber, each of the pair of contacts coupled to a different one of the contact and the spring probe and a container supporting the chamber and containing a cryogenic material therein surrounding the chamber. The semiconductor material is preferably a group II-VI composition, preferably HgCdTe. The contact disposed on the surface portion of the semiconductor material is preferably indium. A support, preferably sapphire, is provided for the sample.

Abstract: A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. However, the present invention patterns this conductive layer, thereby providing a local interconnect with the sheet resistance of the order of one ohm per square. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect level fulfills all of the functions which a buried contact layer could fulfill, and fulfills other functions as well.

Abstract: This is a FET device and the device comprises: a buffer layer 30; a channel layer 32 of doped narrow bandgap material over the buffer layer; and a resistive layer 34 of low doped wide bandgap material over the channel layer, the doping of the channel layer and the resistive layer being such that no significant transfer of electrons occurs between the resistive layer and the channel layer. This is also a method of making a FET device.

Abstract: A two color infrared detector (10) is described comprising a heterojunction diode and a metal insulator semiconductor ("MIS") device. The diode comprises first (12) and second (14) semiconductor regions which are operable to generate electron-hole pairs when struck by infrared radiation having first and second wavelengths respectively. The gate (24) of the MIS device is operable to generate a potential well in the first semiconductor region conjunction with an insulator layer (22).