Abstract: A high swing cascode bias circuit is provided for use within an integrated circuit. The bias circuit utilizes a start up transistor. The use of the start up transistor allows for high swing at the bias circuit outputs even though only one current source is provided from a reference bias circuit. The bias circuit may be powered down in response to a power down control signal. When the bias circuit is activated a plurality of bias signals may be provided to operating circuits of the integrated circuit.

Abstract: A chemical delivery system which utilizes multiple techniques to achieve a suitable chemical purge of the chemical delivery system is provided. A purge sequence serves to purge the manifold and canister connection lines of the chemical delivery system prior to removal of an empty chemical supply canister or after a new canister is installed. More particularly, a purge technique which may utilizes a variety of combinations of a medium level vacuum source, a hard vacuum source, and/or a liquid flush system is disclosed. By utilizing a plurality of purge techniques, chemicals such as TaEth, TDEAT, BST, etc. which pose purging difficulties may be efficiently purged from the chemical delivery system. The chemical delivery system may also be provided with an efficient and conveniently located heater system for heating the chemical delivery system cabinet.

Abstract: A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.

Abstract: A system and method is disclosed for calibrating comparators of an ADC. Individual comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra "proxy" or replacement comparators. More particularly, at periodic intervals a psuedo-random one of the comparators may be disconnected from the standard ADC circuitry for calibration. In order to prevent a significant degradation in the conversion quality, the digital logic downstream of the comparators may be designed to provide the necessary adjustments to accommodate for the removal of one of the comparators. Thus, a calibration technique is provided in which individual comparators are removed from the data conversion path during conversion and the downstream logic adjusts to accommodate for the removal of the comparator. The calibration technique is particularly advantageous for use with optical data storage systems.

Abstract: A circuit is provided for use with analog to digital conversion techniques in sampled amplitude read channel integrated circuits. A common ADC may be utilized for conversion of both high frequency disk data such as user data and servo data, for example, and for low frequency auxiliary data such as, for example, motor back-EMF current signals. The ADC may utilize the relatively low bit accuracy required for the read channel disk data and through oversampling techniques obtain sufficient conversion accuracy to meet the relatively higher precision requirements for the auxiliary data conversion. The auxiliary data is modified by a ramp signal and the ADC is run on a clock generated from a dithered frequency source so that ADC quantization errors may be randomized.

Abstract: A system and method for a data detection circuit is provided in which separate coarse gain amplifiers and fine gain amplifiers are utilized. The coarse gain amplifiers may include drain switching of transistors in order to modify the amplifier gain. More particularly, drain switching may be utilized to selectively switch in and out different differential input transistor pairs and/or different current sources. In this manner the gain of the amplifier may be adjusted to one of a variety of different coarse gain control levels. The coarse gain control provided allows for gain adjustments without significantly decreasing the bandwidth of the amplifier. In a preferred embodiment the system and method may be utilized for data detection circuits utilized in conjunction with optical disks.

Abstract: A system and method is disclosed in which a circuit is provided to improve the settling performance of synthesizers used in read/write channel applications when the synthesizer is required to switch frequencies by a small percentage quickly. This is useful in read channel applications where the clock recovery is performed using an all-digital PLL. A digital timing recovery scheme is utilized in which one data frequency synthesizer provides both write and read frequencies. The read frequency is set higher than the write frequency to allow for oversampling when reading data from the storage medium. When changing from a write to read frequency or vice-versa the frequency synthesizer rapidly settles to the new frequency. The frequency synthesizer includes a phase locked loop which utilizes a controllable oscillator. The phase locked loop divisors are changed to obtain the desired frequency changes. An input signal to the controllable oscillator is also changed in order to obtain the rapid settling times.

Abstract: A system and method is provided having a flash analog-to-digital converter (ADC) that includes an input signal buffer, a plurality of identical voltage comparators, and a reference generator. A clock signal defines the time instances at which the instantaneous input signal voltage is compared against a plurality of reference voltages generated by the reference generator. The individual comparator consists of a an integrating amplifier stage followed by an analog latching stage and a digital latch. The integrating amplifier input is allowed to track the input signal continuously. The amplifier output voltage is forced to a voltage close to zero before each conversion cycle is initiated by the ADC clock. At the beginning of the conversion cycle, the amplifier output is released and its voltage will follow an excursion related to the integral of the input of the amplifier. At a predefined time moment later, the analog latch is activated.

Abstract: A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.

Abstract: An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.

Abstract: A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data presented at the output of the delta sigma modulator. In particular, filter operations may be enabled only for a given digital state, for example, a digital 1 state. Thus, the filter operations may be enabled only for typically half of the bits from the serial bit stream and the power usage of the digital filter is significantly reduced.

Abstract: A system and method for regulating the voltage at an input node of a varying current demand circuit is provided. The input node may be a power supply node and the varying current demand circuit may be a controllable oscillator. In addition, a frequency synthesizer may be formed from a phase locked loop which includes the controllable oscillator and a voltage control circuit. The voltage control circuit may receive an input control signal that varies as the current demand of the controllable oscillator varies. In response to the input control signal, the voltage control circuit may provide a more stable voltage supply to the controllable oscillator even as the current demands of the oscillator vary widely. The input control signal may be generated by generating a signal from the loop path of the phase locked loop. The frequency synthesizer may be utilized in a data storage system data detection circuit, such as for example, a data detection circuit used for recovering data from an optical disk.

Abstract: An amplifier circuit having four variable impedance nodes is provided. The amplifier has split transconductance current paths. Each half of the amplifier has two such current paths and each current path has a node which may be either a high impedance or low impedance node. Connected between the two nodes is a transistor which is utilized in driving the nodes to their either high or low impedance state. The invention is particularly useful in a folded cascode amplifier used for driving loud speakers. However, the circuitry may also be used in other amplifiers or other applications. Further, the linearity of the amplifier's transfer curve may be improved to provide improved performance for high resistive loads. Thus, a class A-B amplifier is provided which can drive a wide range of resistive loads with varying linearity requirements. Moreover, the amplifier can be programmed to provide a high linearity region depending on the desired application.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.