Abstract: An apparatus stacks semiconductor wafers and spacers and clamps them in an axial alignment for mounting in a semiconductor wafer edge polishing machine. After edge polishing, the apparatus separates the wafers and spacers and delivers them respectively into separate cassettes for further processing or recycling.

Abstract: Generally, and in one form of the invention, a composite signal decoder (60) is disclosed which does not require synchronizing the sampling rate to the phase of the incoming pilot signal. Curve fitting filter (126) up-samples and interpolates the incoming composite signal (A) using a bank of coefficient filters selected from filter coefficient bank storage (122) by Bank Selector (124). Bank selector (124) operates in response to a phase offset value produced by phase calculator (112). Because curve fitting filter (126) need not be synchronous with the incoming pilot signal, the output sample rate can be asynchronous from the input sample rate. Other devices, systems and methods are also disclosed.

Abstract: System for processing teletext information which makes it possible practically without any delay to reproduce the information pages transmitted by television transmitters on the screen of a television set, the updated state of the reproduced pages being ensured. The system includes a buffer (46) for the data signals corresponding in each case to an information page. Furthermore, it includes a microprocessor (32) which receives the buffered data signals and within the period required for the transmission of an information page stores them in a main memory (24) for all information pages. In dependence upon a page request signal entered by a user a control unit (26) generates a control command for the microprocessor (32) which causes the latter to fetch from the main memory (24) the page requested by the page request signal and supply it to an image processor (42) which generates from the data signals the signals necessary for the reproduction on the screen.

Abstract: The device comprises at least one printed circuit board (11,12) on which is fixed a heightening board (15) comprising at least one opening (16) for forming with the surface of the printed circuit board (12) located in facing relation to the opening, the bottom and the lateral walls of a cavity (17) for at least one integrated circuit (18) connected with the printed circuit carried by the board defining the bottom of the cavity by means of conductive wires (19). The cavity containing the integrated circuit is filled with a resin (22) completely covering the integrated circuit. The printed circuit board (11,12) is cut on its periphery along a line of through holes (23) provided with a metal coating (24) and connected to printed conductors of the board, metallized grooves (23,24) resulting from the cutting constituting connection terminals of the device.

Abstract: A lead frame (10) is connected over an integrated circuit (40) by adhesives (42) and (44). Each lead conductor (16) and (18) of the lead frame (10) has the identical geometric area in order to provide identical capacitances. A metal shield may be provided on adhesives (42) and (44) to provide noise shielding for the integrated circuit (40).

Abstract: A resonant mirror is disclosed which comprises a deflectable mirror generally planar with the stop surface of a substrate. The mirror is suspended adjacent the top surface by at least two supporting elements. At least one supporting element is displaced from an edge of the mirror. The supporting elements, being collinear, define an axis of rotation about which the mirror may oscillate to steer incident light through an angle.

Abstract: A pulse width modulating circuit including a shift register and a subtraction circuit, with first and second binary counters respectively connected to the outputs of the shift register and the subtraction circuit, and a logic circuit connected to the outputs of the binary counters. Pulse width control data bits are input to the shift register and the subtraction circuit. The shift register processes the pulse width control data bits by shifting them one bit to the right and dividing the control data bits in half. The output of the shift register is also connected to the subtraction circuit and provides one-half of the pulse width control data bits to the inputs of the subtraction circuit and the first counter. A load signal is respectively applied to the first and second binary counters which are responsive thereto for sensing the left and right edges of a pulse width modulation signal based upon the outputs from the shift register and the subtraction circuit.

Abstract: The invention is an improved layout for integrated circuits employing local interconnect pads, particularly six-transistor SRAM circuits, comprising a local interconnect pad which electrically bridges two segments of a conducting line and an active device, and a method for employing the layout.

Abstract: A structure for and method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30. Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

Abstract: The invention relates to such semiconductor devices comprising: a wiring layer with a predetermined pattern formed over a major surface of a semiconductor substrate through an insulating film, a diffusion layer formed under a contact hole formed in said insulating film in an adjacent region of the wiring layer, and a conductive layer deposited into said contact hole in a state of being connected to said wiring layer.

Abstract: Circuitry is provided for controlling current in an electronic circuit by determining a rating of the electronic circuit in response to a measured propagation of a signal during a fixed period of time and by controlling current through an output node of the electronic circuit in response to the rating. The current may be controlled by magnitude or by rate of change with respect to time. By controlling current in response to the rating, timing disparities between and within electronic circuits are reduced, and signal noise in an electronic circuit is reduced by lowering unnecessary amounts of current driving the output node and/or by lowering unnecessarily high DI/DT rates of change in current driving the output node.

Abstract: In a method and circuitry for variable single transition counting, a count signal (178) is provided on a count line. A direction control bit (264) is output on a direction control line. A significant bit (278e) is output on a significant bit line. A first single transition count (278a-d) is incremented in response to the count signal (178) and to the direction control bit (264) having an incrementing logic state. The first single transition count (278a-d) is decremented in response to the count signal (178) and to the direction control bit (264) having a decrementing logic state. The first single transition count (278a-d) and the significant bit (278e) together form a second single transition count (278a-e). The second single transition count (278a-e) is compared against a preselected value (296), and a comparison signal (320) is output in response to the second single transition count (278a-e) being equal to the preselected value (296 ).

Abstract: An operational amplifier (10) is provided which includes a differential input stage (18) for receiving differential signals. A differential loop (30, 64), (86) amplifies said differential signals. The amplified differential signals are output on a pair differential output terminals (80, 84). A common mode loop (54), (30, 64) maintains the mean voltage of the amplified differential signals at a preselected value.

Abstract: A chassis for a portable printer wherein the structural members of the chassis not only makes the chassis more rigid, but each serves a functional role.

Abstract: A memory card has a housing including an interior chamber and a top metal cover. A substrate is located in the interior chamber and carries printed circuit leads, packaged semiconductor devices connected to selected printed circuit leads, and a connector connected to selected printed circuit leads. The packaged semiconductor devices are spaced from the top metal cover and a thermal coupler is located between the top metal cover and the packaged semiconductor devices for coupling heat generated by the packaged semiconductor devices to the top metal cover.

Abstract: An integrated circuit device is disclosed. The device includes a first leadframe power supply bus and a second leadframe power supply bus that each have portions separate from and adjacent to one another that lie between a first plurality of leadfingers and a second plurality of leadfingers. An electronic device is connected to the first leadframe power supply bus and to the second leadframe power supply bus. Another electronic device can be connected to the first leadframe power supply bus and to the second leadframe bus. Exemplary of the electronic devices are a de-coupling capacitor and a capacitor for high frequency noise suppression. A semiconductor die is attached to the power supply busses. A substance encapsulates the components so that an integrated semiconductor chip is formed. A method of making an integrated circuit device is also disclosed.

Abstract: A memory cell comprises a semiconductor pillar comprising an inversion layer formed on a side wall of the pillar. A conductive capacitor of the memory cell comprises a first electrode formed by the inversion layer. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region comprising the inversion layer. The gate is coupled to a control line partially overlying a top end of the pillar.

Abstract: A system and method for X-Y alignment and tracking of moving targets having angular displacement with a fiber optic sensing surface comprising a sensor (5, 6, 17) comprising a sensing array (5) for providing an indication of the position of a beam of radiation incident on the sensing array, a radiation source for providing a beam of radiation (laser), means for simultaneously directing said beam of radiation along two separate paths (4), inhibiting circuitry for alternately inhibiting travel of the beam of radiation in each of the separate paths (13, 14), reflecting means (3, 15) in each path deflecting the beam of radiation in each path to the sensing array and responsive to the position of a beam of radiation incident on the sensing array for altering the position of the beam relative to the sensing array and circuitry responsive to the position of the beam for providing a desired object parameter indication (18, 19).

Abstract: A static random access memory timing scheme is disclosed in which the latching of a sense amplifier is derived from substantially the same point in the a timing chain as is the precharge/equalization signal, which is derived from the row address transition detection signal (as is the word line gating signal). Fan-in is minimized so as to allow good immunity to gamma dot and parameter variations.

Abstract: A digital crossbar switch designed to facilitate easy and flexible interconnection of up to 8 data ports. The device includes 8 bidirectional ports, each 8 bit wide. Interconnection of the ports is controlled by 32 stored control memory locations associated with each port. The controlling memory locations can be changed dynamically without interfering with data flow. Additional program flexibility can be achieved by providing each port with a 16 word first-in first-out data buffer. The capability to bit reverse the data on any of the ports is also provided to simplify the interconnection of busses from different architectures. The device is fully expandable to wider busses, has extensive test capability and a master reset is provided for system initialization.