Abstract: A mixer circuit is described having three transistors connected in series across the supply rails. Two of the transistors carry signals, and these are arranged to be close to but not in saturation so that the circuit can operate with very low supply voltages.

Abstract: In one embodiment, mirroring communication from a second source storage device to a second target storage device in a data mirroring system is disabled when mirroring communication from a first source storage device to a first target storage device is disabled. In another embodiment, information is stored in a data mirroring system identifying at least one subset of a plurality of mirrored source storage devices for which a consistent representation of data is desired to be maintained on at least one corresponding subset of a plurality of target storage devices. In yet another embodiment, at least one of a plurality of mirrored source storage devices is placed in one of a first state, a second state, and a third state. In response to a source storage system receiving a write-requesting command chain directed to a mirrored source storage device in the first state, the command chain is permitted to commit and data written by the command chain is transferred to a corresponding target storage device.

Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

Abstract: Process for producing metrological structures particularly for direct measurement of errors introduced by alignment systems, whose peculiarity consists in performing, on a same substrate, metrological alignment markings and processed alignment markings according to arrays of preset numerical size.

Abstract: A three-terminal insulated-gate power electronic device includes a first, bipolar power transistor and a second, insulated-gate transistor forming a darlington pair. The bipolar power transistor has a first electrode, a second electrode, and a control electrode respectively connected to a first electrode of the insulated-gate transistor and to a first external terminal of the three-terminal device, to a second external terminal of the three-terminal device, and to one second electrode of the insulated-gate transistor.

Abstract: A testing contactor is provided for testing small-size semiconductor devices with large currents at high frequencies. Each semiconductor device to be tested has a plurality of leads. The testing contactor includes a plurality of first electric contact elements. A first Kelvin contact for a lead is formed of a first electric contact element in contact with the lead. The testing contactor further includes a plurality of second electric contact elements and a plurality of electric connection elements. An electric connection element in contact with the lead effectively extends the lead. A second Kelvin contact is formed of a second electric contact element and an electric connection element, the second electric contact element in contact with the electric connection element and the electric connection element in contact with the lead.

Abstract: A digital phase comparator supplies digital values corresponding to the phase shifts between a first signal having a duty cycle of approximately 0.5 and a second signal. The comparator includes a one-way counter initialized at the frequency of the first signal and clocked by a clock signal having a high frequency with respect to the frequency of the first and second signals. A logic gate enables the counter when the first and second signals are in respective predetermined states. A phase shift is considered to be zero when it corresponds approximately to one half of the counter's capacity.

Abstract: A fixed impedance load is provided with a signal having a variable frequency F from a line capable of supplying a variable available power. The device comprises a pulse width modulator that operates at frequency F and supplies the load with pulses, the width of which varies in the same way as the available power, so that the consumed power on the line remains lower than the available power.

Abstract: An application specific integrated circuit that comprises a central processing unit and a plurality of devices which are dependent on the application of the integrated circuit and are connected to the central processing unit. At least one shift register is provided by connecting in series elementary cells each mounted on a respective line corresponding to an input/output line of the central processing unit, each cell being able to inject into its respective line a value entered serially through the shift register, and further being able to sample the value of the binary signal carried by its respective line with a view to a reading of this value through the shift register. A method is provided for using the shift register to test the makeup of the application specific integrated circuit, or an application program executing on the central processing unit.

Abstract: A ring oscillator buffer stage, supplied by an adjustable current source of an asymmetrical current controlled ring oscillator, is provided for amplifying the output of the ring oscillator. The frequency of the ring oscillator varies as a function of a control signal. The buffer stage includes; a plurality of current controlled buffers, supplied by currents which are controlled in correspondence with the control signal, for amplifying the output of the oscillator; and a buffer for amplifying the output of the current controlled buffers for providing a full-swing output signal with a duty cycle of approximately 50%.

Abstract: A signal processing circuit that includes a differential amplifier and an integrator. The differential amplifier receives at a first input a signal to process and at a second input an offset compensation signal provided by the integrator. The integrator includes a differential transconductance amplifier receiving an output voltage of the signal processing circuit at a first input and a reference voltage at a second input; a capacitor having a first terminal connected to the output of the transconductance amplifier and a second terminal connected to a fixed voltage; and a voltage follower receiving the voltage at the first terminal of the capacitor and providing the offset compensation signal.

Abstract: The disclosure relates to the methods and devices that enable series type buses to be protected against the consequences of a short-circuit in the decentralized units connected to this bus. There are provided means to detect the equalization of the potentials of the data wires and means enabling the disconnection, under the control of these detection means, of the decentralized unit responsible for the short circuit. A device is also provided to short circuit the supply wires of the bus according to a predetermined sequence in order to inform the central processing unit of the disconnection of said decentralized unit. The disclosure enables the protection of the central processing unit and of the decentralized units, connected to the bus, that are not malfunctioning.