Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein the metal layers are vertically disposed within a substitute. A layer of a dielectric medium is disposed between the metal layers and a third metal layer is spaced apart from the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is spaced apart from the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.

Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed.

Abstract: A masking method for use in a silicide formation process is disclosed herein which prevents an oxide etching solution from tunneling under a photoresist masking layer and damaging oxide spacers not intended to be etched. This process may be used during the formation of a bipolar or MOS transistor formed in an isolated silicon island. A mask opening used to etch exposed oxide spacer portions is made to not expose any parasitic oxide spacers formed along an edge of the isolated silicon island. In this way, an oxide etch solution is prevented from tunneling along the parasitic oxide spacer and reaching any intersecting oxide spacers not intended to be etched. The desired oxide spacers will thus be intact to properly isolate silicide portions formed over exposed silicon and polysilicon surfaces.

Abstract: A digital clock divider is capable of dividing a clock frequency n by N.5, where N is an integer, and includes a closed loop of flip-flops numbering twice N.5, and an additional flip-flop to which the clock signal is applied through an inverter, the output signal of the additional flip-flop is 180.degree. out of phase with a signal from a flip-flop of the closed loop. The 180.degree. out-of-phase signals are applied to an OR2 gate, the output signal of which has a frequency of n (clock signal) divided by N.5.

Abstract: To exchange data in the same position in the hybrid ring control cycles in two FDDI-II rings, the cycles of the different rings are phase and frequency aligned. To achieve phase alignment, a hybrid multiplexer in one of the rings monitors the cycles on the other ring and starts a cycle when the hybrid multiplexer detects a starting delimiter on the other ring. In order to achieve frequency alignment, 8 KHz references produced by two hybrid multiplexers on the two respective rings are provided to a circuit that selects one of the references to determine the frequency for synchronizing cycle outputs of both hybrid multiplexers.

Abstract: A test circuit (200) furnishes a low battery level signal on the basis of a comparison between a first ratio of the battery potential when the battery (206) is unloaded and a second ratio of the loaded battery potential. The battery test circuit includes a potential divider (210), a comparator (250) and a potential sampler including a storage element (240), a controller (260), a control line (266) and a switch (268). The potential divider is coupled to the battery and includes a first tap (226) and a second tap (224). The potential sampler, which includes a storage element (240), is coupled to the first tap through a switch (268) so that a first ratiometric portion of the unloaded battery voltage is stored on the storage element. The comparator has a first input that is coupled to the storage element and a second input that is coupled to the second tap.

Abstract: A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K.

Abstract: An improved Class A amplifier has an enhanced slew rate response at high frequencies. A positive feedback path is connected from the output of the amplifier to a point on the gain path. The feedback path includes a capacitor, a resistor and a transistor, the resistor being connected between the base and emitter of the transistor. At relatively high frequencies, the voltage drop across the resistor causes the transistor to turn on, forming a buffered positive feedback path through an additional resistor. The amount of feedback is controlled by the second resistor in the feedback path. In the preferred embodiment, dual feedback paths are connected between the output terminal and different points in the gain path.

Abstract: An integrated circuit voltage regulator employs a PNP pass transistor to produce a low dropout voltage. Saturation in the pass transistor produces excessive substrate current which appears in the form of wasted current which lowers the regulator efficiency. A current conducted by the sat catcher circuit is employed to avoid pass transistor saturation. The sat catcher is controlled dynamically so the dropout voltage is minimized and the voltage regulator maintains good performance at high regulator output currents.

Abstract: A process for forming field effect transistors having self-aligned source/drain contact includes: forming an gate overlying a portion of a semiconductor; forming a first sidewall spacer on the gate; forming a source/drain region in the semiconductor; depositing a conductive layer over the semiconductor so that a step is formed in the conductive layer in a region overlying the gate and the first sidewall spacer; forming a second sidewall spacer on the step; forming a protective layer over a portion of the conducting layer not covered by the second sidewall spacer; removing the second sidewall spacer to expose a portion of the conductive layer but leave covered a portion of the conductive layer underlying the protective layer; and removing the exposed portion of the conductive layer to leave a portion of the conductive layer in contact with the source/drain region and electrically isolated from the gate. The portion of the conductive layer left is the self-aligned contact.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: An improved method for simulating the surface contours of a layer of material to be formed over a base structure using a string algorithm is described. The method of the string algorithm includes the steps of defining old surface points along the base structure, defining a set of possible new surface points, and defining a set of orderly array of points, from the set of new surface points, which define the surface contours of the simulated layer of material formed over the base structure.

Abstract: A monolithic switching regulator on chip loop frequency compensation circuit is described. An op-amp is provided with a conventional small frequency compensation capacitor, which determines its unity gain frequency and an input resistor. The op-amp incorporates 100% negative feedback. When driven at a frequency that is below its unity gain frequency the noninverting input of the op-amp displays a capacitance having a value on the order of nanofarads, which value would ordinarily require an excessive chip area if fabricated as an actual capacitor. This capacitance value is useful in the on chip loop frequency compensation of a switching regulator where the switching frequency is operated at about 150 kHZ.

Abstract: A ROM filter includes a number of ROMs, each of which is programmed to hold data relating to several pulse response curves during only a particular time interval. As data are read into the filter, data pertaining to a particular pulse response curve are addressed in each of the ROMs. The outputs of the ROMs are connected to an adder, which adds the data read from the ROMs and passes it through a digital-to-analog converter. In this arrangement, the ROMs are required to store only the data relating to the pulse response curves during a particular interval. These data are added together in real time in an adder which is external to the ROM. With this structure the area of the ROM can be significantly reduced, as compared with ROM filters in which the addition is programmed into the ROM.

Abstract: An anti-lock braking system includes three integrated circuits (an integrated voltage regulator and two different microcontrollers) which perform different functions but share the tasks of detecting malfunctions and shutting down the system when malfunctions are detected. The two different microcontrollers perform different functions, have different circuitry, and execute different software. Typically, a first microcontroller receives wheel sensor signals, calculates wheel velocities and accelerations, and operates mechanical devices which control braking. A second microcontroller executes the main anti-lock braking software and determines from the velocities and accelerations when brakes should be released. All of the integrated circuits monitor each other and the other elements of the anti-lock braking system to detect malfunctions. Multiple shut down methods are provided so that a single chip failure can be safely handled.

Abstract: A switcher mixer architecture creates special effects such as a dissolve or a wipe from one priority structure of the elements of an image scene to a completely different prioritized ordering of those same or even other elements that comprise the same or a different image scene. The special effect can be thought of as a "priority transition" in the sense that the priority of a set of input image signals can be transitioned from that of a "from" image to that of a "to" image. The switcher mixer architecture eliminates a soft border artifact from the special effect by allowing a border to be given its own priority as though the border were a separate image input as well as to couple together (1) a source, or "from," image having one or more elements; (2) a destination, or "to," image having one or more elements, which could be the same or different than the "from" image elements; and (3) a border image for separating the source image and the destination image in an image display.

Abstract: An arrangement involving apparatus and process damps vibrations, for example, rotary or linear vibrations, in a member to be damped, for example, in a supply tension arm forming part of a tape transport of a digital cassette recording system. The arrangement includes a limited angle torquer motor having an output connected to the member such that the presence of the detected vibrations to be damped imparts corresponding vibrations to the shaft (output) of the motor which, in turn, results in a corresponding back EMF voltage within the motor. A servo circuit connected to the input of the motor is designed to be responsive to the back EMF voltage within the motor, actually to an emulated version of the back EMF voltage, for driving the motor in a way to thereby damp the vibrations within the motor shaft which, in turn, damps the rotary or linear vibrations within the member itself. Approximately 20dBs of attenuation in vibration at the resonant frequency has been shown.

Abstract: A keyed, true-transparency combine and keyer receive a plurality of image information signals V.sub.i, each having a corresponding input key signal Bk.sub.i, over a respective channel. The image signals are dynamically ranked in a prioritized order, even on a field-by-field basis. However, rather than switch the individual image signals as the prioritized order changes, the order of the channels is dynamically and switchably interchanged within a keyer by switchably interchanging a plurality of substantially identical keyer units while generating a plurality of processed true transparency image key signals Pk.sub.i. While there may be some structural distinctions among the keyer units, there is commonalty of function among the keyer units within the keyer. The keyer also generates processed background key signals Pk.sub.B. The keyer units are switchably changed to produce true transparency processed key signals such that processed key signal Pk.sub.